US 12,748,597 B2 · Processor supporting position-independent addressing

Abstract

A processor may implement position-independent memory addressing by providing load and store instructions that include position-independent addressing modes. A memory address may contain a normalized pointer, where the memory address stores a normalized memory address that, when added to an offset previously determined for the memory address, defines another memory address. The position-independent addressing mode may also support invalid memory addresses using a reserved value, where a load instruction providing the position-independent addressing mode may return a NULL value or generate an exception when determining that the stored normalized memory address is equal to the reserved value and where a store instruction providing the position-independent addressing mode may store the reserved value when determining that the memory address is an invalid or NULL memory address.

Claims20

Dependent claims

A method, comprising:

executing, by a processor, an instruction of an application, wherein the instruction comprises a position-independent addressing mode, and wherein the executing comprises:
obtaining a first offset for a memory location identified by the instruction from a hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location;
and
resolving, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location.

1 more element

A system, comprising:

a memory subsystem comprising a persistent memory and a memory storing an instruction of an application, the instruction indicating a position-independent addressing mode;
and
a processor different from the memory subsystem, the processor comprising a hardware lookup table that stores a first offset for a memory location and configured to execute the instruction, wherein to execute the instruction, the processor is configured in hardware circuitry to:
obtain the first offset from the hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location;
and
resolve, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location.

3 more elements

Dependencies are inferred from the claim text.

Processor supporting position-independent addressing

Life of this patent

Processor supporting position-independent addressing

Life of this patent

Abstract

Claims20