Processor-cache system and method
AssigneeShanghai Xin Hao Micro Electronics Co. Ltd.
InventorsKenneth Chenghao Lin, Haoqi Ren
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Abstract
A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.
Claims13
A digital system, comprising:
- an execution unit coupled to a data memory containing data to be used in operations of the execution unit;
- a level-zero (L0) memory coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory;
- and
- an address generation unit configured to generate address information for addressing the L0 memory,
- wherein the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.
Dependencies are inferred from the claim text.