US 6,829,696 B1 · Data processing system with register store/load utilizing data packing/unpacking · patentgrep

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Abstract

A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory (42) and a central processing unit core (44) with at least one register file (76). The core is responsive to a load instruction (e.g., LDW_BH[U] instruction 184) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction 198) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data. A single store or load instruction can perform all of the tasks that used to take several instructions, while at the same time conserving memory space.

Claims39

Dependent claims

A data processing system comprising:

a memory comprising a plurality of memory locations;
and
a central processing unit core comprising at least one register file with a plurality of registers, said core connected to said memory for loading data from and storing data to said memory locations, said core responsive to a load instruction to retrieve data words from said memory and parse said data words over selected parts of two data registers in said at least one register file, said parse comprising interleaved unpacking the lower and higher half-words of each of said two data words into corresponding pairs of data registers.

A data processing system comprising:

a memory comprising a plurality of memory locations;
and
a central processing unit core comprising
a plurality of A functional units,
a plurality of B functional units,
an A register file with a plurality of A registers accessed by corresponding register numbers, each A register capable of serving as a source or destination for any A functional unit,
a B register file with a plurality of B registers accessed by corresponding register numbers, each B register capable of serving as a source or destination for any B functional unit,
a first cross path connected to said A register file and said B functional units permitting any one A register file to be a source for at least one B functional unit,
a second cross path connected to said B register file and said A functional units permitting any one B register file to be a source for at least one A functional unit,
said core connected to said memory for loading data from and storing data to said memory locations, said core responsive to a load instruction to retrieve at least one data word from said memory and parse said at least one data word over selected parts of two data registers including an A register having a first register access number and a second B register having said first register access number.

7 more elements

A data processing system comprising:

a memory comprising a plurality of memory locations;
and
a central processing unit core comprising
a plurality of A functional units,
a plurality of B functional units,
an A register file with a plurality of A registers accessed by corresponding register numbers, each A register capable of serving as a source or destination for any A functional unit,
a B register file with a plurality of B registers accessed by corresponding register numbers, each B register capable of serving as a source or destination for any B functional unit,
a first cross path connected to said A register file and said B functional units permitting any one A register file to be a source for at least one B functional unit,
a second cross path connected to said B register file and said A functional units permitting any one B register file to be a source for at least one A functional unit,
said core connected to said memory for loading data from and storing data to said memory locations, said core responsive to a store instruction to concatenate data from selected parts of two data registers including an A register having a first register access number and a second B register having said first register access number into at least one data word.

7 more elements

A data processing system comprising:

a memory comprising a plurality of memory locations;
and
a central processing unit core comprising
a plurality of A functional units,
a plurality of B functional units,
an A register file with a plurality of A registers accessed by corresponding register numbers, each A register capable of serving as a source or destination for any A functional unit,
a B register file with a plurality of B registers accessed by corresponding register numbers, each B register capable of serving as a source or destination for any B functional unit,
a first cross path connected to said A register file and said B functional units permitting any one A register file to be a source for at least one B functional unit,
a second cross path connected to said B register file and said A functional units permitting any one B register file to be a source for at least one A functional unit,
said core connected to said memory for loading data from and storing data to said memory locations, said core responsive to a load instruction to retrieve at two data words from said memory and parse said data words over selected parts of four data registers including a first A register having a first even register access number, a second A register having a second odd register access number one more that said first even register access number, a first B register having said first even register access number, and a second B register having said second odd register access number.

7 more elements

A data processing system comprising:

a memory comprising a plurality of memory locations;
and
a central processing unit core comprising
a plurality of A functional units,
a plurality of B functional units,
an A register file with a plurality of A registers accessed by corresponding register numbers, each A register capable of serving as a source or destination for any A functional unit,
a B register file with a plurality of B registers accessed by corresponding register numbers, each B register capable of serving as a source or destination for any B functional unit,
a first cross path connected to said A register file and said B functional units permitting any one A register file to be a source for at least one B functional unit,
a second cross path connected to said B register file and said A functional units permitting any one B register file to be a source for at least one A functional unit,
said core connected to said memory for loading data from and storing data to said memory locations, said core responsive to a store instruction to concatenate data from selected parts of four data registers including a first A register having a first even register access number, a second A register having a second odd register access number one more that said first even register access number, a first B register having said first even register access number, and a second B register having said second odd register access number into two data words.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/687,540Filed 13 Oct 2000 · us provisional application
Priority: 30 Dec 1999
Granted: 7 Dec 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/30032
To perform operations on data operands: movement instructions, e.g. move, shift, rotate, shuffle
G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations
G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask

Family

Application60/173,761Us provisional application · filed 30 Dec 1999
US 6,829,696 B1This patent

From the US filing history. Foreign family members aren’t listed.

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