System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization

A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first hardware architecture being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second hardware architecture;

• wherein the changeable internal hardware organization of the dynamically reconfigurable processing unit comprises a data operate unit having a data port and a control input, for performing operations upon data, the data port of the data operate unit coupled to the data port of the memory and the control input coupled to receive control signals;
• and wherein the data operate unit comprises:
• a switch having a data port, a control input, a feedback input, and an output, for selectively routing data between said data port, said feedback input, and said output, said data port of the switch coupled to the data port of the memory, said control input of the switch coupled to receive control signals;
• a store/align unit having an input, an output, and a control input, for storing data, the input of the store/align unit coupled to the output of the switch, the control input of the store/align unit coupled to receive control signals;
• and
• a data operate circuit having an input, an output, and a control input, for performing data computations, the input of the data operate circuit coupled to the output of the store/align unit, the output of the data operate unit coupled to the feedback input of the switch, and the control input of the data operate logic coupled to receive control signals.

A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first hardware architecture being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second hardware architecture;

• wherein the changeable internal hardware organization of the reconfigurable processing unit comprises an address operate unit having a control input, an address input, and an output, for performing operations upon addresses, the address input coupled to a data port of a memory, and the output of the address operate unit coupled to an address input of the memory, and the control input of the address operate unit coupled to receive control signals;
• and wherein the address operate unit comprises:
• a switch having a data port, a control input, a feedback input, and an output, for selectively routing addresses between said data port, said feedback input, and said output in response to control signal receive on said control input, said data port of the switch coupled to the data port of the memory;
• a store/count unit having an input, an output, and a control input, for storing data, the input of the store/count unit coupled to the output of the switch, the control input of the store/count logic coupled to receive control signals;
• and
• an address operate circuit having an input, an output, and a control input, for performing address computations, the input of the address operate circuit coupled to the output of the store/count unit, the output of the address operate circuit coupled to the feedback input of the switch, and the control input of the address operate unit coupled to receive control signals.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• the first communication device further having a first data port and a second data port, the system further comprising:
• a second reconfigurable processing unit for executing program instructions to process data, the second reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions;
• a second communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the second reconfigurable processing unit, the input of the second communication device coupled to the output of the second reconfigurable processing unit, and the output of the second communication device coupled to the input of the second reconfigurable processing unit;
• and
• an interconnect means for routing data and having a plurality of communication channels, the first data port of the first communication device, the second data port of the first communication device, the first data port of the second communication device, and the second data port of the second communication device each coupled to one of the plurality of communication channels.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• the first communication device further having a first data port and a second data port, the system further comprising:
• a non-reconfigurable processing unit having a predefined architecture for executing a program of instructions formed from a single instruction set, the non-reconfigurable processing unit having an input, an output;
• a second communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the non-reconfigurable processing unit, the input of the second communication device coupled to the output of the non-reconfigurable processing unit, the output of the second communication device coupled to the input of the non-reconfigurable processing unit;
• and
• an interconnect means for routing data and having a plurality of communication channels, the first data port of the first communication device, the second data port of the first communication device, the first data port of the second communication device, and the second data port of the second communication device each coupled to one of the plurality of communication channels.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• a second reconfigurable processing unit for executing program instructions to process data, the second reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions;
• a second communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the second reconfigurable processing unit, the input of the second communication device coupled to the output of the second reconfigurable processing unit, and the output of the second communication device coupled to the input of the second reconfigurable processing unit;
• and
• an interconnect means for routing data and having a plurality of communication channels, the first data port of the first communication device, the second data port of the first communication device, the first data port of the second communication device, and the second data port of the second communication device each coupled to one of the plurality of communication channels.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• a memory storing a first configuration data set that corresponds to a first instruction set architecture for a serial instruction processor and a second configuration data set that corresponds to a second instruction set architecture for a parallel instruction processor, and wherein the first reconfigurable processing unit can be selectively configured as one from the group of a serial instruction processor and a parallel instruction processor in response to signals from the memory, the first reconfigurable processing unit being coupled to the memory;
• wherein the first reconfigurable processing unit is coupled to the memory by a plurality of signal lines and a first number of said plurality of signal lines forming address lines, a second number of said plurality of signal lines forming control lines and a third number of said plurality of signal lines forming data lines, the first number, second number and third number of said plurality of signal lines being reconfigurable and set according to a configuration data set utilized by the first reconfigurable processing unit.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• wherein the changeable internal hardware organization of the first reconfigurable processing unit comprises a reconfigurable data operate unit having a data port and a control input, for performing operations upon data, the data port of the data operate unit coupled to a data port of a memory and the control input coupled to receive control signals;
• and wherein the reconfigurable data operate unit comprises:
• a switch having a data port, a control input, a feedback input, and an output, for selectively routing data between said data port, said feedback input, and said output, said data port of the switch coupled to the data port of the memory, the control input of the switch coupled to the first control output of the instruction fetch unit;
• a store/align unit having an input, an output, and a control input, for storing data and data computation results, the input of the store/align unit coupled to the output of the switch, the control input of the store/align unit coupled to the first control output of the instruction fetch unit;
• and
• a data operate circuit having an input, an output, and a control input, for performing data computations, the input of the data operate circuit coupled to the output of the store/align unit, the output of the data operate circuit coupled to the feedback input of the switch, and the control input of the data operate circuit coupled to the first control output of the instruction fetch unit.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• wherein the changeable internal hardware organization of the first reconfigurable processing unit comprises a reconfigurable address operate unit having a control input, an address input, and an output, for performing operations upon addresses, the address input coupled to a data port of a memory, and the output of the address operate unit coupled to an address input of the memory, and the control input of the address operate unit coupled to receive control signals;
• and wherein the reconfigurable address operate unit comprises:
• a switch having a data port, a control input, a feedback input, and an output, for selectively routing addresses between said data port, said feedback input, and said output, said data port of the switch coupled to the data port of the memory, the control input of the switch coupled to the first control output of the instruction fetch unit;
• a store/count unit having an input, an output, and a control input, for storing data, the input of the store/count unit coupled to the output of the switch, the control input of the store/count logic coupled to the second control output of the instruction fetch unit;
• an address operate circuit having an input, an output, and a control input, for performing address computations, the input of the address operate circuit coupled to the output of the store/count unit, the output of the address operate circuit coupled to the feedback input of the switch, and the control input of the address operate unit coupled to the second control output of the instruction fetch unit.

A system for dynamically reconfigurable computing comprising:

• a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set;
• and
• a first communication device having an input and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;
• wherein the first reconfigurable processing unit comprises:
• a reconfigurable instruction fetch unit having a data input, a first control output, and a second control output, for sequencing instruction execution operations within the first reconfigurable processing unit, the data input coupled to a data port of a memory;
• a reconfigurable data operate unit having a data port and a control input, for performing operations upon data, the data port of the data operate unit coupled to the data port of the memory and the control input coupled to the first control output of the instruction fetch unit;
• and
• a reconfigurable address operate unit having a control input, an address input, and an output, for performing operations upon addresses, the control input of the address operate unit coupled to the second control output of the instruction fetch unit, the address input coupled to the data port of the memory, and the output of the address operate unit coupled to an address input of the memory.