Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register

A data processing system comprising

• a data memory having a data port for transferring data words having a first data size and an address port for receiving an address, said data memory storing data words having a second data size smaller than said first data size at a plurality of address locations, said data memory including a plurality of write strobe inputs for each addressable memory location of said second data size within data words of said first data size, said data memory enabled for writing data into corresponding individual addressable memory locations of said second data size within said data words of said first data size when active and disabled from writing data into corresponding individual addressable memory locations of said second data size within data words of said first data size when inactive;
• a data processor including
• a data port of said first data size connected to said data port of said data memory;
• an address generator connected to said address port of said data memory for generating an address, said address generator supplying said generated address to said address port of said data memory;
• a plurality of data registers for storing data of a third data size larger than said second data size;
• and
• a data alignor connected to said data port of said data processor, said address generator and said plurality of data registers, said data alignor repeating data recalled from a selected one of said plurality of data registers of a selected processor data size a number of times to fill said data port of said data processor if said selected processor data size is less than said first data size, said data alignor enabling selected one or ones of said write strobes dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator.

In a data processing system including a data memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than said first data size and a plurality of data registers, the method of data transfer comprising the steps of:

• generating an address in the address generator employing a selected one of a plurality of address registers in calculation of said address;
• storing an indication of a processor data size in each of a plurality of qualifier registers, said processor data size being no greater than said first data size and no less than said second data size, each qualifier register corresponding to one and only one of the address registers;
• supplying said address generated by the address generator to the data memory;
• receiving a data word of said first data size corresponding to said address;
• and
• storing data of said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address into a selected one of said data registers, if said selected processor data size is smaller than said first data size selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator and aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers.

In a data processing system including a data memory storing data words having a first data size, said data memory including a plurality of write strobe inputs for each of a plurality of subsets of a second data size smaller than said first data size within data words of said first data size, said data memory enabled for writing data into corresponding individual addressable memory locations within said data words of said second data size when a corresponding write strobe is active and disabled from writing data into corresponding individual addressable memory locations when a corresponding write strobe is inactive, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than said first data size and a plurality of data registers, the method of data transfer comprising the steps of:

• selecting a processor data size no larger than said first data size and no smaller than said second data size;
• supplying an address generated by the address generator to the data memory;
• repeating data recalled from a selected one of said plurality of data registers of said selected processor data size a number of times to fill a data word of said first data size if said selected processor data size is less than said first data size;
• enabling selected one or ones of said write strobes dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator.

A data processing system comprising:

• a data memory having a data port for transferring data words having a first data size and an address port for receiving an address, said data memory storing data words having a second data size smaller than said first data size at a plurality of address locations;
• a data processor including
• a data port of said first data size connected to said data port of said data memory;
• an address generator connected to said address port of said data memory for generating an address, said address generator supplying said generated address to said address port of said data memory, said address generator including
• a plurality of address registers,
• a plurality of index address registers,
• a plurality of qualifier registers each corresponding to one and only one of said plurality of address registers, each of said plurality of qualifier registers storing an indication of either a zero extend mode or a sign extend mode,
• an arithmetic unit having a first input connected to said plurality of address registers, a second input connected to said plurality of index address registers, said arithmetic unit forming an arithmetic combination of data stored in a selected one of said plurality of address registers and data stored in a selected one of said plurality of index registers as said address;
• a plurality of data registers for storing data of said third data size;
• and
• a data alignor connected to said data port, said address generator and said plurality of data registers for receiving a data word of said first data size from said data memory via said data port and storing data of a selected processor data size not greater than said first data size and not less than said second data size into a selected one of said data registers, if said selected processor data size is smaller than said first data size said data alignor
• selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator,
• aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers,
• storing "0's" in most significant bits of said selected one of said plurality of data registers if said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said zero extend mode, and
• storing bits corresponding to a most significant bit of said selected processor data size in most significant bits of said selected one of said plurality of data registers if said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said sign extend mode.

In a data processing system including a data memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than said first data size and a plurality of data registers, the method of data transfer comprising the steps of:

• generating an address in the address generator employing a selected one of a plurality of address registers in calculation of said address;
• storing an indication either a zero extend mode or a sign extend mode of in each of a plurality of qualifier registers, each qualifier register corresponding to one and only one of the address registers;
• supplying said address generated by the address generator to the data memory;
• receiving a data word of said first data size corresponding to said address;
• storing data of said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address into a selected one of said data registers, if said selected processor data size is smaller than said first data size selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator;
• aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size;
• storing "0's" in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said zero extend mode;
• and
• storing bits corresponding to a most significant bit of said selected processor data size in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said sign extend mode.