DRAM with high bandwidth interface that uses packets and arbitration

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates, comprising:

• a memory array, coupled with a memory array controller, that decodes, arbitrates between, and executes memory array access commands, and generates memory array access responses;
• and
• a high bandwidth data interface, coupled with the memory array and the memory array controller, comprising;
• a unidirectional input port, a unidirectional output port, a packet buffer, and an interface controller that includes a receiver section and a transmitter section,
• said unidirectional input port is coupled with the packet buffer and the receiver section, and receives an input data stream comprising memory array access commands, forwarding data and an input clock signal,
• said unidirectional output port is coupled with the packet buffer and the transmitter section, and transmits an output data stream comprising memory array access responses, forwarding data and an output clock signal,
• said receiver section is coupled with the packet buffer and the memory array controller, and decodes and controls flow of the input data stream from the input port to the packet buffer, and to the memory array and the memory array controller,
• said transmitter section is coupled with the packet buffer and the memory array controller, and controls flow of the output data stream from the packet buffer to the output port, and
• said packet buffer is coupled between the input and output ports and the memory array, and stores the memory array access commands prior to servicing by the memory array and the memory array controller, and stores the memory array access responses and the forwarding data prior to servicing by the transmitter section, and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller or memory array.

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates, comprising:

• a plurality of memory arrays, coupled with a memory array controller, that decode, arbitrate between, and execute memory array access commands, and generate memory array access responses;
• and
• a high bandwidth data interface, coupled with the plurality of memory arrays and the memory array controller, comprising;
• a unidirectional input port, a unidirectional output port, a packet buffer, and an interface controller that includes a receiver section, and a transmitter section,
• said unidirectional input port is coupled with the packet buffer and the receiver section, and receives an input data stream comprising memory array access commands, forwarding data and an input clock signal,
• said unidirectional output port is coupled with the packet buffer and the transmitter section, and transmits an output data stream comprising memory array access responses, forwarding data and an output clock signal,
• said receiver section, is coupled with the packet buffer and the memory array controller, and decodes and controls flow of the input data stream from the input port to the packet buffer, and to the plurality of memory arrays and the memory array controller,
• said transmitter section, is coupled with the packet buffer and the memory array controller, and controls flow of the output data stream from the packet buffer to the output port, and
• said packet buffer is coupled between the input and output ports and the plurality of memory arrays, and stores the memory array access commands prior to servicing by the plurality of memory arrays and the memory array controller, and stores the memory array access responses and the forwarding data prior to servicing by the transmitter section, and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller or plurality of memory arrays.

A high bandwidth data interface, comprising:

• a data path, an interface controller, a slave port and a packet buffer;
• said data path is coupled with the packet buffer and interface controller, and receives an input data stream through an input port and transmits an output data stream through an output port;
• said interface controller is coupled with the packet buffer, and controls flow of the input and output data streams within the high bandwidth data interface;
• and
• said packet buffer is coupled between the data path and the slave port, and temporarily stores data from the input and output data streams and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller.

A method for processing a stream of data received by a device as a plurality of input packets, said method comprising the steps of:

• receiving an input packet, composed of a plurality of fixed bit length data fields, through an input port;
• decoding the input packet, and processing the input packet by either executing the input packet as a request to the device, or forwarding the input packet, as an output packet, to another device through a forwarding path directly linking the input port to an output port, according to information conveyed by the plurality of fixed bit length data fields;
• and
• when the input packet is determined to be a request to the device, generating an output packet composed of a plurality of fixed bit length data fields, wherein at least one of the output packet's fixed bit length data fields corresponds with at least one of the fixed bit length data fields of one of the input packets.