G06F 9/30003
Arrangements for executing specific machine instructions
Official title: {Arrangements for executing specific machine instructions}
G06F9/30003 (Arrangements for executing specific machine instructions) appears on 14,824 US grants and 14,862 published applications in this corpus.
Search patents in G06F- Granted patents
- 14,824
- Published applications
- 14,862
- Assignees
- 1,777
- Inventors
- 17,016
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 8 | 0 |
| 1977 | 12 | 0 |
| 1978 | 8 | 0 |
| 1979 | 6 | 0 |
| 1980 | 9 | 0 |
| 1981 | 14 | 0 |
| 1982 | 13 | 0 |
| 1983 | 16 | 0 |
| 1984 | 22 | 0 |
| 1985 | 17 | 0 |
| 1986 | 26 | 0 |
| 1987 | 22 | 0 |
| 1988 | 31 | 0 |
| 1989 | 33 | 0 |
| 1990 | 33 | 0 |
| 1991 | 41 | 0 |
| 1992 | 43 | 0 |
| 1993 | 76 | 0 |
| 1994 | 74 | 0 |
| 1995 | 90 | 0 |
| 1996 | 148 | 0 |
| 1997 | 190 | 0 |
| 1998 | 301 | 0 |
| 1999 | 295 | 0 |
| 2000 | 246 | 0 |
| 2001 | 275 | 51 |
| 2002 | 208 | 264 |
| 2003 | 205 | 257 |
| 2004 | 239 | 391 |
| 2005 | 211 | 320 |
| 2006 | 239 | 293 |
| 2007 | 252 | 296 |
| 2008 | 254 | 413 |
| 2009 | 235 | 380 |
| 2010 | 309 | 295 |
| 2011 | 321 | 326 |
| 2012 | 287 | 331 |
| 2013 | 359 | 561 |
| 2014 | 361 | 643 |
| 2015 | 430 | 636 |
| 2016 | 757 | 700 |
| 2017 | 699 | 785 |
| 2018 | 666 | 820 |
| 2019 | 844 | 1106 |
| 2020 | 969 | 1109 |
| 2021 | 1070 | 1036 |
| 2022 | 978 | 926 |
| 2023 | 923 | 849 |
| 2024 | 866 | 788 |
| 2025 | 660 | 626 |
| 2026 | 433 | 660 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Vector bitwise rotations6 Oct 2026US 12,754,736 B2Imagination Technologies Limited
- Embedded gateway system with data prefetch mechanism6 Oct 2026US 12,754,737 B2Airoha Technology (Suzhou) Limited
- Interrupt handling6 Oct 2026US 12,754,760 B2BlackBerry Limited
- Systems and methods for scalable and coherent memory devices6 Oct 2026US 12,754,840 B2Samsung Electronics Co., Ltd.
- System and method for persisting hardware transactional memory transactions to persistent memory6 Oct 2026US 12,754,842 B1
- Control method and chip8 Oct 2026US 2026/0310463 A1Smarter Silicon (Shanghai) Technologies Co., Ltd.
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Information processing system, information processing apparatus, information processing method, and non-transitory computer readable medium8 Oct 2026US 2026/0310474 A1Toyota Jidosha Kabushiki Kaisha
- Processor-in-memory (pim) command truth table definition8 Oct 2026US 2026/0310628 A1QUALCOMM Incorporated
- Efficient matrix multiply and add with a group of warps1 Oct 2026US 2026/0299943 A1NVIDIA Corporation
Most cited
By later US patents
- Packet processing system including a policy engine having a classification unit624US 6,157,955 AIntel Corporation · 2000
- Method and system for efficient matrix multiplication in a SIMD processor architecture531US 7,873,812 B12011
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Algorithm mapping, specialized instructions and architecture features for smart memory computing432US 7,546,438 B22009
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013