Embedded gateway system with data prefetch mechanism

Abstract

An embedded gateway system includes a processor, a first memory, a second memory, and a data prefetch circuit. The processor is used to execute a first program. The first memory is used to store a first data. The first memory and the second memory are external memories of the processor, and access latency of the second memory is lower that access latency of the first memory. The data prefetch circuit is used to perform a first data prefetch operation upon the first memory for reading a first prefetched data from the first memory and writing the first prefetched data into the second memory. Before a time point at which the processor executes a data access code segment of the first program to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetched data.

Dependencies are inferred from the claim text.