Back to results
US 12,754,760 B2Granted
Interrupt handling
AssigneeBlackBerry Limited
InventorElad Lahav
Life of this patent
Estimating the term…
Abstract
In some examples, a system includes one or more hardware processors, an interrupt service thread to handle an interrupt, and a kernel scheduler to schedule the interrupt service thread as part of a collection of threads to be scheduled.
Claims20
A system comprising:
- one or more hardware processors;
- a plurality of threads executable on the one or more hardware processors and comprising interrupt service threads to handle respective interrupts, wherein the plurality of threads are assigned respective priorities, and wherein a first thread associated with an application program has a first priority that is higher than a second priority of a first interrupt service thread of the interrupt service threads;
- and
- a kernel scheduler executable on the one or more hardware processors to:
- schedule execution of the plurality of threads based on the respective priorities assigned the plurality of threads, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts, wherein an interrupt source of a given interrupt is associated with a plurality of interrupt service threads, wherein the kernel scheduler masks the interrupt source while processing the given interrupt, wherein the interrupt source remains masked when the kernel scheduler exits interrupt processing, wherein an interrupt mask count for the interrupt source is incremented for each interrupt service thread of the plurality of interrupt service threads associated with the interrupt source, and wherein the interrupt source is unmasked after a matching number of calls to unmask the interrupt source are made by the plurality of interrupt service threads associated with the interrupt source.
2 more elements
A method of a system comprising one or more hardware processors, comprising:
- receiving, by a scheduling executive of an operating system (OS) kernel executing on the one or more hardware processors, a call from a first thread of an application program, wherein the first thread has a first priority, and wherein the system comprises a plurality of threads comprising the first thread of the application program and interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities such that the first priority of the first thread of the application program is higher than a second priority of a first interrupt service thread of the interrupt service threads;
- associating the interrupt service threads with respective interrupt sources;
- receiving, by the scheduling executive executing on the one or more hardware processors, an indication of an interrupt from an interrupt source of the interrupt sources, wherein the first interrupt service thread is executable on a first hardware processor to handle the interrupt from the interrupt source;
- and
- scheduling, by the scheduling executive executing on the one or more hardware processors, execution of the plurality of threads based on the respective priorities assigned the plurality of threads, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts, wherein the interrupt source is associated with a plurality of interrupt service threads, wherein the scheduling executive masks the interrupt source while processing the interrupt, wherein the interrupt source remains masked when the scheduling executive exits interrupt processing, wherein an interrupt mask count for the interrupt source is incremented for each interrupt service thread of the plurality of interrupt service threads associated with the interrupt source, and wherein the interrupt source is unmasked after a matching number of calls to unmask the interrupt source are made by the plurality of interrupt service threads associated with the interrupt source.
2 more elements
A non-transitory machine-readable storage medium comprising instructions that upon execution cause a system to:
- receive, at a scheduling executive of an operating system (OS) kernel, a call from a non-interrupt service thread, wherein the non-interrupt service thread has a first priority, and wherein the system comprises a plurality of threads comprising the non-interrupt service thread and interrupt service threads, the interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities such that the first priority of the non-interrupt service thread is higher than a second priority of a first interrupt service thread of the interrupt service threads;
- receive, at the scheduling executive, a notification of an interrupt from an interrupt source, wherein the interrupt is associated with the first interrupt service thread executable on a first hardware processor to handle the interrupt;
- and
- schedule, by the scheduling executive, the non-interrupt service thread and the first interrupt service thread based on the first priority and the second priority, wherein the scheduling comprises preempting the first interrupt service thread with the non-interrupt service thread based on the non-interrupt service thread having the first priority that is higher than the second priority, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts, wherein the interrupt source is associated with a plurality of interrupt service threads, wherein the scheduling executive masks the interrupt source while processing the interrupt, wherein the interrupt source remains masked when the scheduling executive exits interrupt processing, wherein an interrupt mask count for the interrupt source is incremented for each interrupt service thread of the plurality of interrupt service threads associated with the interrupt source, and wherein the interrupt source is unmasked after a matching number of calls to unmask the interrupt source are made by the plurality of interrupt service threads associated with the interrupt source.
1 more element
Dependencies are inferred from the claim text.