G06F 9/3005
To perform operations for flow control
Official title: {to perform operations for flow control}
G06F9/3005 (To perform operations for flow control) appears on 2,100 US grants and 2,082 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,100
- Published applications
- 2,082
- Assignees
- 445
- Inventors
- 3,428
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 3 | 0 |
| 1982 | 4 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 4 | 0 |
| 1989 | 7 | 0 |
| 1990 | 5 | 0 |
| 1991 | 7 | 0 |
| 1992 | 8 | 0 |
| 1993 | 10 | 0 |
| 1994 | 10 | 0 |
| 1995 | 15 | 0 |
| 1996 | 19 | 0 |
| 1997 | 28 | 0 |
| 1998 | 53 | 0 |
| 1999 | 49 | 0 |
| 2000 | 41 | 0 |
| 2001 | 58 | 5 |
| 2002 | 23 | 37 |
| 2003 | 27 | 35 |
| 2004 | 26 | 47 |
| 2005 | 38 | 48 |
| 2006 | 32 | 32 |
| 2007 | 36 | 35 |
| 2008 | 33 | 65 |
| 2009 | 24 | 54 |
| 2010 | 48 | 38 |
| 2011 | 51 | 46 |
| 2012 | 24 | 44 |
| 2013 | 45 | 81 |
| 2014 | 48 | 109 |
| 2015 | 47 | 104 |
| 2016 | 131 | 106 |
| 2017 | 118 | 155 |
| 2018 | 103 | 101 |
| 2019 | 131 | 144 |
| 2020 | 138 | 141 |
| 2021 | 142 | 115 |
| 2022 | 110 | 107 |
| 2023 | 104 | 128 |
| 2024 | 114 | 101 |
| 2025 | 102 | 98 |
| 2026 | 73 | 106 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- In-flight incremental processing6 Oct 2026US 12,756,768 B2Intel Corporation
- Tunneling of peripheral-bus protocol traffic over coherent fabric and chip-to-chip or die-to-die bus15 Sep 2026US 12,737,314 B2Mellanox Technologies, Ltd.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Descriptor-based hardware prefetcher1 Oct 2026US 2026/0299948 A1Advanced Micro Devices, Inc.
- Simulation apparatus, simulation method, and non-transitory computer readable medium1 Oct 2026US 2026/0299951 A1Renesas Electronics Corporation
- Systems and methods for dynamically switching between branch prediction modes1 Oct 2026US 2026/0299956 A1Advanced Micro Devices, Inc.
- Prediction entry allocation24 Sep 2026US 2026/0288461 A1Arm Limited
- Method and apparatus for parallel pointer operations17 Sep 2026US 2026/0277609 A1Electronics and Telecommunications Research Institute
Most cited
By later US patents
- Computer processor with an efficient means of executing many instructions simultaneously306US 5,471,593 A1995
- Apparatus and method for program level parallelism in a VLIW processor233US 6,170,051 AMicron Technology, Inc. · 2001
- Hierarchical priority branch handling for parallel execution in a parallel processor218US 4,833,599 AMultiflow Computer, Inc. · 1989
- Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer215US 5,721,855 AIntel Corporation · 1998
- Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies205US 4,847,755 AMCC Development, Ltd. · 1989