Systems and methods for updating memory side caches in a multi-GPU configuration

An apparatus comprising:

• an interface to a coherent chip-to-chip interconnect;
• a first graphics processor having a second memory and associated with a second cache, wherein the coherent chip-to-chip interconnect is configured to enable coherent access to a first memory by the first graphics processor, the first memory is associated with a general-purpose processor having a plurality of processor cores, the general-purpose processor is coupled with the first graphics processor via the coherent chip-to-chip interconnect, and the general-purpose processor has a first cache;
• and
• memory management circuitry coupled with first graphics processor and the interface to the coherent chip-to-chip interconnect, the memory management circuitry operable to maintain a unified virtual memory for the first graphics processor and the general-purpose processor, wherein the coherent chip-to-chip interconnect is operable to enable coherency between the first cache and the second cache for the unified virtual memory and the memory management circuitry is configured to enable the general-purpose processor to cache data from the second memory in the first cache at cache line granularity.

A multi-chip module comprising:

• a first packaged integrated circuit comprising a general-purpose processor including a plurality of processor cores and a first cache, wherein the general-purpose processor is associated with a first memory;
• a coherent chip-to-chip interconnect coupled with the general-purpose processor;
• a second packaged integrated circuit coupled with the first packaged integrated circuit via the coherent chip-to-chip interconnect, the second packaged integrated circuit including a first graphics processor having a second memory, wherein the coherent chip-to-chip interconnect is configured to enable coherent access to the first memory by the first graphics processor;
• and
• memory management circuitry coupled with the coherent chip-to-chip interconnect, the memory management circuitry to enable the general-purpose processor to cache data from the second memory in the first cache at cache line granularity, wherein the general-purpose processor and the first graphics processor have a unified virtual address space.

A method for accessing memory in a heterogeneous processing system, the method comprising:

• providing a first integrated circuit comprising a general-purpose processor including a plurality of processor cores and a first cache, wherein the general-purpose processor is associated with a first memory;
• coupling a coherent chip-to-chip interconnect with the first cache;
• coupling a second integrated circuit with the first integrated circuit via the coherent chip-to-chip interconnect, the second integrated circuit including a first graphics processor having a second memory;
• configuring the coherent chip-to-chip interconnect to enable coherent access to the first memory by the first graphics processor;
• and
• enabling the general-purpose processor to cache data from the second memory in the first cache at cache line granularity using memory management circuitry coupled with the coherent chip-to-chip interconnect, wherein the general-purpose processor and the first graphics processor have unified virtual memory.