US 5,471,593 AGranted

Computer processor with an efficient means of executing many instructions simultaneously

OwnerMichael H. Branigininventor

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Abstract

To increase the performance of a pipelined processor executing instructions, conditional instruction execution issues and executes instructions, including but not limited to branches, before the controlling conditions may be available and makes the decision to update the destination as late as possible in the pipeline. Conditional instruction execution is further improved by a condition code mask field in instructions to choose those condition code bits to be involved in the decision; by a set condition code flag to enable or disable the setting of a condition code; by stale condition code handling to determine if the logically previous conditionally executing instruction was successful or unsuccessful in setting the condition code and to conditionally execute accordingly; by multiple condition codes so that independent instruction sequences can use condition codes in parallel; and by condition code reservation stations to capture a needed condition code as soon as it becomes available and hold that captured value until needed, thus freeing the condition code as soon as possible for use by other instructions. Moving the conditional decision from the point of instruction issue to the point of instruction completion permits branch instructions to be eliminated in many cases; permits conditionally executing instructions directly in line; permits filling the branch umbra following a delayed branch with conditionally executing instructions; and reduces the latency from condition code generation to condition code use.

Claims12

Dependent claims

A method of executing instructions in a pipelined processor comprising:

a conditional execution decision logic pipeline stage and a least one instruction execution pipeline stage prior to said conditional execution decision logic pipeline stage;
at least one condition code;
said instructions including branch instructions and non-branch instructions and each instruction including opcodes specifying operations, operand specifiers specifying operands, and conditional execution specifiers;
said pipelined processor further including at least one write pipeline stage for writing the result(s) of each instruction to specified destination(s);
at least one of the instructions including a means for specifying writing said condition code with a condition code result;
the conditional execution decision logic pipeline stage performing a boolean algebraic evaluation of the condition code and said conditional execution specifier and producing an enable-write with at least two states, true and false;
and
said enable-write when true enabling and when those disabling the writing of instruction results at said write pipeline stage;
said method further comprising the steps of:
fetching source operands specified by said operand specifiers;
performing the operation specified by said opcode;
fetching the condition code, when specified by the conditional execution specifier, at the pipeline stage immediately preceding the conditional execution decision logic pipeline stage;
operating the conditional execution decision logic pipeline stage, when specified by the conditional execution specifier, to determine the enable-write using the boolean algebraic evaluation;
writing said non-branch instruction results to a destination specified by the operand specifiers of the executing instruction and writing condition code results to the condition code when specified by the operand specifiers of the executing instruction, if the enable-write is true;
and
discarding or not writing the non-branch instruction results and discarding or not writing the condition code, if the enable-write is false.

13 more elements

A pipelined processor for executing instructions comprising:

a conditional execution decision logic pipeline stage, a least one instruction execution pipeline stage prior to said conditional execution decision logic pipeline stage;
at least one condition code;
said instructions including branch instructions and non-branch instructions and including opcodes specifying operations, operand specifiers specifying operands, and conditional execution specifiers;
the pipelined processor further including at least one write pipeline stage for writing the result(s) of each instruction to specified destination(s);
at least one of the instructions including a means for specifying writing said condition code with a condition code result;
the conditional execution decision logic pipeline stage performing a boolean algebraic evaluation of the condition code and said conditional execution specifier and producing an enable-write with at least two states, true and false;
said enable-write when true enabling and when false disabling the writing of instruction results at said write pipeline stage;
fetching means for fetching source operands specified by said operand specifiers;
operating means for performing the operation specified by said opcode;
condition code fetching means for fetching the condition code, when specified by the conditional execution specifier, at the pipeline stage immediately preceding the conditional execution decision logic;
the conditional execution decision logic pipeline stage, when specified by the conditional execution specifier, determining the enable-write using the boolean algebraic evaluation;
writing means for writing said non-branch instruction results to a destination specified by the operand specifiers and writing to the condition code when specified, if enable-write is true;
and
said writing means further for discarding or not writing the non-branch instruction results and discarding or not writing the condition code, if enable-write is false.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/184,355Filed 21 Jan 1994 · continuation
Priority: 11 Dec 1989
Granted: 28 Nov 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/30018
To perform operations on data operands: bit or string instructions
G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask
G06F 9/30069
To perform operations for flow control: instruction skipping instructions, e.g. SKIP
G06F 9/30072
Arrangements for executing specific machine instructions: to perform conditional operations, e.g. using predicates or guards