Hierarchical priority branch handling for parallel execution in a parallel processor

Apparatus for simultaneously executing a plurality of sequential instructions in a parallel processing data multiprocessor, said multiprocessor having a plurality of arithmetic processing units, comprising:

• means for processing a plurality of said instructions to be executed in parallel and having a hierarchical priority for denoting a tentative order of execution of said instructions,
• each processing unit comprising:
• means for executing a selected plurality of said instructions during a single machine cycle, said selected plurality of instructions including at most one branch instruction,
• a first and a second branch bank register set,
• means employing said branch bank register sets for determining whether test conditions associated with a branch instruction are satisfied,
• means for simultaneously and independently determining a target program counter address for said branch instruction,
• means responsive to other processing units for determining if the processing unit has the highest priority branch instruction with a satisfied branch test condition, and
• means for setting a next instruction address equal to the determined target program counter address of the test condition satisfied highest priority branch instruction,
• means for determining a fall-through program counter address if an instruction branch is not taken, and
• means, if no instruction address is set, for setting said next instruction address equal to said fall-through address.

A multiway branch apparatus for executing a sequence of instruction groups, each instruction of a group being executed in a parallel processing fashion, each group able to contain a plurality of branch instructions, the apparatus having a plurality of processing clusters, each cluster having at least one arithmetic logic unit, the apparatus comprising:

• means for directing each branch instruction of a group to a different processing cluster,
• said processing clusters being adapted and interconnected for executing said branch instructions of said instruction group in parallel during a single machine cycle,
• each processing cluster having, for executing a branch instruction:
• means responsive to the instruction data directed thereto for testing during said execution whether the branch instruction has a test condition associated therewith which is true,
• means for determining, during said execution, the relative priority of its branch instruction with respect to the branch instructions of other processing clusters,
• means for simultaneously determining, during said execution, a target program counter address for the branch instruction, and
• means for directing to each other processing cluster a branch signal indicating the relative priority and condition branch value for the directing cluster;
• a global controller for determining a fall-through program counter address if a branch is not taken, and
• means for addressing a program counter bus with the program counter value for the next instruction dependent upon the priority values and the condition branch results.