Apparatus and method for program level parallelism in a VLIW processor

A multi-issue processor having multiple functional units, each functional unit having one or more pipeline stages, each pipeline stage having access to a primary resource, said processor comprising:

• one or more secondary resources provided as a selection of resources accessible by selected functional units;
• a thread indicator signal designating from which instruction stream an instruction was dispatched, said selected functional units responsive to said thread indicator signal;
• a dispatch unit which concurrently accepts multiple instructions from each of a plurality of instruction streams and which, in a given cycle, selectively sends instructions from multiple instruction streams to said functional units, said dispatch unit asserting said thread indicator signal to select a set or resources to be accessed by said functional units responsive to said thread indicator signal while carrying out said instruction;
• and
• a thread indicator delay line which propagates said thread indicator signal so that, during each clock cycle, different stages of said functional units are responsive to said thread indicator signal to selectively use said selected set of resources.

A multi-issue processor having multiple functional units, each functional unit having one or more pipeline stages, each pipeline stage having access to a primary resource, said processor comprising:

• one or more secondary resources provided as a selection of resources accessible by selected functional units;
• a thread indicator signal designating from which instruction stream said instruction was dispatched, at least the functional unit to which said instruction is dispatched being responsive to said thread indicator signal;
• a dispatch unit which concurrently accepts multiple instructions from each of a plurality of instruction streams and which, in a given cycle, selectively sends instructions from multiple instruction streams to said functional units, said dispatch unit asserting said thread indicator signal to select a set or resources to be accessed by said functional units responsive to said thread indicator signal while carrying out said instruction;
• and
• a delay circuit operative to store one or more delayed versions of said thread indicator signal and to selectively apply one or more of said stored versions to different stages of a selected functional unit during a selected clock cycle so that different pipeline stages of said selected functional unit may use said selected set of resources.

A multi-issue processor having multiple functional units, each functional unit having one or more pipeline stages, each pipeline stage having access to a primary resource, said processor comprising:

• one or more secondary resources provided as a selection of resources accessible by selected functional units;
• a thread indicator signal designating from which instruction stream said instruction was dispatched, at least the functional unit to which said instruction is dispatched being responsive to said thread indicator signal;
• a dispatch unit which concurrently accepts multiple instructions from each of a plurality of instruction streams and which, in a given cycle, selectively sends instructions from multiple instruction streams to said functional units, said dispatch unit asserting said thread indicator signal to select a set of resources to be accessed by said functional units responsive to said thread indicator signal while carrying out said instruction;
• and
• a thread indicator delay line which propagates said thread indicator signal so that, during each clock cycle, different stages of said function units are responsive to said thread indicator signal to selectively use said selected set of resources.