Method and system for efficient matrix multiplication in a SIMD processor architecture

An execution unit for performing matrix multiplication of a first matrix with a second matrix using a plurality of computational units in parallel, the execution unit comprising:

• a vector register file with multiple ports including a plurality of vector registers wherein each of said plurality of vector registers storing N vector elements, and said vector register file containing a first source vector as a first operand, a second source vector as a second operand, and a control vector register as a third operand of a vector instruction;
• means for mapping elements of said first source vector and said second source vector in accordance with said control vector register, said first source vector elements comprising a numbered column of said first matrix, and said second source vector elements comprising a respective numbered row of said second matrix;
• a vector computational unit, comprising said plurality of computational units, wherein mapped elements of source vectors provide paired vector elements as inputs to each of said plurality of computational units;
• a vector accumulator, wherein output of said vector computational unit is stored or accumulated with previous partial results;
• wherein at least one vector multiply instruction is executed for performing matrix multiplication of first column of said first matrix with first row of said second matrix with a single clock cycle throughput;
• and
• wherein a plurality of vector multiply-accumulate instructions are executed for performing matrix multiplication of second and subsequent columns of said first matrix with respective second and subsequent rows of said second matrix and accumulation of partial results by said vector accumulator, each of said plurality of vector multiply-accumulate instructions is executed with single clock cycle throughput.

A method for performing matrix multiplication of a first matrix with a second matrix calculating multiple values of an output matrix in parallel, the method comprising:

• a) performing matrix multiplication of first column of said first matrix with first row of said second matrix in a first set of steps performed by using a vector multiply instruction in a single clock cycle, said first set of steps comprising:
• storing at least first column of said first matrix in a first source vector, and storing at least first row of said second matrix in a second source vector;
• pairing elements of said first source vector and said second source vector as source value pairs for vector operations, wherein said first source vector and said second source vector are mapped in accordance with matrix multiplication requirement;
• and
• performing a vector multiply operation of said paired elements of said first source vector and said second source vector, and storing output of said vector multiply operation in an output vector;
• b) performing matrix multiplication of second column of said first matrix with second row of said second matrix in a second set of steps performed by using a vector multiply-accumulate instruction in a single clock cycle, said second set of steps comprising:
• storing at least second column of said first matrix in said first source vector, and storing at least second row of said second matrix in said second source vector;
• repeating the step of pairing elements;
• performing a vector multiply-accumulate operation by way of multiplying said paired elements of said first source vector and said second source vector, summing output of said vector multiply-accumulate operation with respective elements of said output vector, and storing output of summing in said output vector;
• and
• c) repeating said second set of steps for the rest of the columns of said first matrix and the rest of the rows of said second matrix.