Apparatus and method for efficient prefetching using secure error correction code (ecc) encoding
OwnerDavid M. Durham, Sergej Deutsch +1inventors
InventorsDavid M. Durham, Sergej Deutsch, Christoph Dobraunig
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Abstract
An apparatus and method for efficient prefetching using secure ECC encodings. For example, one embodiment of an apparatus comprises: front end circuitry to fetch and decode a plurality of instructions; execution circuitry to execute the plurality of instructions, the execution circuitry to fetch a first memory line from a system memory, the first memory line comprising an identifier for a second memory line, the identifier at least partly encoded in a hidden error correction code (ECC) symbol; and prefetch circuitry to prefetch the second memory line responsive to reading the identifier from the first memory line.
Claims20
A processor, comprising:
- front end circuitry to fetch and decode instructions;
- execution circuitry to execute the instructions, the execution circuitry to fetch a first memory line from a system memory, the first memory line comprising an identifier associated with a second memory line, the identifier at least partly encoded in a hidden error correction code (ECC) symbol;
- and
- prefetch circuitry to prefetch the second memory line responsive to reading the identifier from the first memory line.
A method, comprising:
- fetching and decoding a plurality of instructions;
- executing, by execution circuitry, the plurality of instructions, the execution circuitry to fetch a first memory line from a system memory, the first memory line comprising an identifier for a second memory line, the identifier at least partly encoded in a hidden error correction code (ECC) symbol;
- and
- prefetching, by prefetch circuitry, the second memory line responsive to reading the identifier from the first memory line.
A machine-readable medium comprising program code which, when executed by one or more processors, is to cause the one or more processors to perform operations, comprising:
- fetching and decoding a plurality of instructions;
- executing, by execution circuitry, the plurality of instructions, the execution circuitry to fetch a first memory line from a system memory, the first memory line comprising an identifier for a second memory line, the identifier at least partly encoded in a hidden error correction code (ECC) symbol;
- and
- prefetching, by prefetch circuitry, the second memory line responsive to reading the identifier from the first memory line.
Dependencies are inferred from the claim text.