Technique for handling ordering constrained access operations

A method of handling ordering constrained access operations in an apparatus having processing circuitry to perform operations, the method comprising:

• employing instruction decoder circuitry to decode instructions to control the processing circuitry to perform the operations specified by the instructions;
• employing a set of registers to hold data values for access by the processing circuitry;
• causing the instruction decoder circuitry, in response to an ordering constrained access instruction used to access multiple data values, and providing register indication information and memory address information, to control the processing circuitry to perform a sequence of access operations, where each access operation causes a data value from amongst the multiple data values to be moved between an associated register determined from the register indication information and an associated memory address determined from the memory address information;
• and
• determining, responsive to an ordering indication derived from the ordering constrained access instruction, an order in which the multiple data values are to be accessed when performing the sequence of access operations;
• wherein the ordering indication is used to identify an order in which the memory addresses associated with the multiple data values are to be accessed, to thereby determine the order in which the multiple data values are to be accessed.

A computer program product comprising a non-transitory computer-readable storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment, comprising:

• processing program logic to perform operations;
• instruction decode program logic to decode instructions to control the processing program logic to perform the operations specified by the instructions;
• and
• register emulating program logic to emulate a set of registers to hold data values for access by the processing program logic;
• wherein the instruction decode program logic is responsive to an ordering constrained access instruction used to access multiple data values, and providing register indication information and memory address information, to control the processing program logic to perform a sequence of access operations, where each access operation causes a data value from amongst the multiple data values to be moved between an associated register determined from the register indication information and an associated memory address determined from the memory address information;
• wherein:
• an ordering indication is derived from the ordering constrained access instruction and used to determine an order in which the multiple data values are to be accessed when performing the sequence of access operations;
• and
• the ordering indication is used to identify an order in which the memory addresses associated with the multiple data values are to be accessed, to thereby determine the order in which the multiple data values are to be accessed.