G06F 30/343
Logical level
G06F30/343 (Logical level) appears on 498 US grants and 400 published applications in this corpus.
Search patents in G06F- Granted patents
- 498
- Published applications
- 400
- Assignees
- 149
- Inventors
- 1,009
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 2 | 0 |
| 1996 | 0 | 0 |
| 1997 | 3 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 2 | 1 |
| 2002 | 1 | 6 |
| 2003 | 2 | 10 |
| 2004 | 8 | 8 |
| 2005 | 5 | 4 |
| 2006 | 7 | 13 |
| 2007 | 7 | 6 |
| 2008 | 18 | 3 |
| 2009 | 16 | 2 |
| 2010 | 11 | 4 |
| 2011 | 14 | 5 |
| 2012 | 12 | 4 |
| 2013 | 14 | 10 |
| 2014 | 23 | 14 |
| 2015 | 26 | 12 |
| 2016 | 25 | 19 |
| 2017 | 32 | 25 |
| 2018 | 30 | 40 |
| 2019 | 50 | 35 |
| 2020 | 43 | 27 |
| 2021 | 33 | 25 |
| 2022 | 29 | 34 |
| 2023 | 27 | 33 |
| 2024 | 15 | 26 |
| 2025 | 22 | 17 |
| 2026 | 18 | 17 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Real time analysis and control for a multiprocessor system29 Sep 2026US 12,748,682 B2HyperX Holdings LLC
- Method and apparatus to enable CPU host-unaware dynamic FPGA reconfiguration25 Aug 2026US 12,717,992 B2Altera Corporation
- Systems and methods for programmable fabric design compilation28 Jul 2026US 12,694,180 B2Altera Corporation
- High-level-synthesis for RISC-V system-on-chip generation for field programmable gate arrays28 Jul 2026US 12,694,181 B2Microsemi SoC Corporation
- Line diagnosis method and apparatus21 Jul 2026US 12,688,345 B2Lenovo (Beijing) Limited
- Programmable Matrix Switch Array for Reconfigurable Circuits27 Aug 2026US 2026/0252772 A1Board of Regents, The University of Texas System
- System and method for predicting power consumption of integrated circuit and method for designing integrated circuit using the same9 Jul 2026US 2026/0195514 A1SK hynix Inc.
- Hardware-based trigger point instrumentation circuit18 Jun 2026US 2026/0170217 A1NXP B. V.
- Circuit Design Visibility in Integrated Circuit Devices14 May 2026US 2026/0134183 A1Altera Corporation
- Method for Transistor Layout Generation Using Graph Neural Network Recursive Model30 Apr 2026US 2026/0119756 A1GenChip.AI Inc.
Most cited
By later US patents
- Frequency driven layout and method for field programmable gate arrays239US 5,659,484 AXilinx, Inc. · 1997
- Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same188US 9,621,173 B12017
- Congestion estimation for programmable logic devices169US 7,992,120 B1Lattice Semiconductor Corporation · 2011
- System and method for configuring a programmable hardware instrument to perform measurement functions utilizing estimation of the hardware implentation and management of hardware resources93US 6,608,638 B1National Instruments Corporation · 2003
- System and method for configuring analog elements in a configurable hardware device82US 7,024,654 B2Anadigm, Inc. · 2006