Congestion estimation for programmable logic devices
AssigneeLattice Semiconductor Corporation
InventorsXinyu Wang, Bo Wang
Life of this patent
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AssigneeLattice Semiconductor Corporation
InventorsXinyu Wang, Bo Wang
Estimating the term…
Various techniques are provided for estimating signal congestion in a programmable logic device (PLD). In one example, a computer-implemented method of estimating signal congestion in routing resources of a PLD is provided. The routing resources comprise a plurality of nodes and a plurality of wires which may be selectively interconnected to provide a plurality of signal paths through the routing resources of the PLD. The method includes determining a plurality of wire congestion values. Each of the wire congestion values identifies a relative likelihood of a corresponding one of the wires being used to provide the signal paths in comparison with the other wires. The method also includes selecting a region of the routing resources. The method further includes determining a congestion density estimate for the region using the wire congestion values associated with the wires of the region.
A computer-implemented method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources comprise a plurality of nodes and a plurality of wires which may be selectively interconnected to provide a plurality of signal paths through the PLD, the method comprising:
A system comprising:
A non-transitory computer readable medium on which are stored computer readable instructions for performing in a computing device a method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources comprise a plurality of nodes and a plurality of wires which may be selectively interconnected to provide a plurality of signal paths through the PLD, the method comprising
Dependencies are inferred from the claim text.