High-level-synthesis for RISC-V system-on-chip generation for field programmable gate arrays

A method, comprising:

• identifying a code stream to be executed by a system-on-a-chip (SoC), the SoC to include an open standard ISA processor and one or more hardware accelerators implemented in reprogrammable hardware;
• from the code stream, identifying a first portion of the code stream to be executed as software by the open standard ISA processor of the SoC and a second portion of the code stream to be executed in the one or more hardware accelerators of the SoC;
• compiling the first portion of the code stream into a binary for execution by the open standard ISA processor of the SoC;
• loading the binary onto the SoC;
• generating a hardware description for the second portion of the code stream to be implemented by the one or more hardware accelerators;
• and
• loading the hardware description onto the SoC;
• wherein the hardware description and the binary are to exchange data during execution of the code stream.

A system-on-a-chip (SoC), comprising:

• an open standard ISA processor;
• one or more hardware accelerators implemented in reprogrammable hardware;
• wherein the open standard ISA processor is to execute a binary generated from a first portion of a code stream;
• a second portion of the code stream is to be implemented by a hardware description in the one or more hardware accelerators;
• wherein the hardware description and the binary are to exchange data during execution of the code stream.