Method for Transistor Layout Generation Using Graph Neural Network Recursive Model

A system comprising:

• a memory storing instructions;
• and
• a processing device, coupled with the memory and configured to execute the instructions, the instructions when executed cause the processing device to:
• receive a netlist of an integrated circuit from an electronic design automation tool, the netlist including a description of electronic components, including transistors and electrical connectivity;
• identify transistors from the netlist as nodes for representing each transistor as a node in a network;
• create a graph neural network that connects nodes identified from the netlist, each node in the graph neural network represents parasitic extraction data contact points of transistors, the graph neural network including at least one million nodes;
• generate node embeddings for the graph neural network using a generative adversarial network as well as generating an initial order of node embeddings;
• evaluate the initial order of node embeddings using the generative adversarial network and parasitic extraction data, the generative adversarial network creating a modified order of node embeddings that is closer to predetermined design parameter values of at least performance and power compared to the initial order of node embeddings;
• generate a physical layout design based on the modified order of the node embeddings;
• and
• output the physical layout design to a memory store.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to:

• receive a netlist of an integrated circuit from an electronic design automation tool, the netlist including a description of electronic components, including transistors and electrical connectivity;
• identify transistors from the netlist as nodes for representing each transistor as a node in a network;
• create a graph neural network that connects nodes identified from the netlist, each node in the graph neural network represents parasitic extraction data contact points of transistors, the graph neural network including at least one million nodes;
• generate node embeddings for the graph neural network using a generative adversarial network as well as generating an initial order of node embeddings;
• evaluate the initial order of node embeddings using the generative adversarial network and parasitic extraction data, the generative adversarial network creating a modified order of node embeddings that is closer to predetermined design parameter values of at least performance and power compared to the initial order of node embeddings;
• generate a physical layout design based on the modified order of the node embeddings;
• and
• output the physical layout design to a memory store.