G06F 30/331
With hardware acceleration
Official title: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F30/331 (With hardware acceleration) appears on 1,006 US grants and 766 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,006
- Published applications
- 766
- Assignees
- 271
- Inventors
- 1,872
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 4 | 0 |
| 1994 | 3 | 0 |
| 1995 | 9 | 0 |
| 1996 | 6 | 0 |
| 1997 | 12 | 0 |
| 1998 | 20 | 0 |
| 1999 | 18 | 0 |
| 2000 | 17 | 0 |
| 2001 | 16 | 4 |
| 2002 | 14 | 14 |
| 2003 | 12 | 13 |
| 2004 | 19 | 22 |
| 2005 | 10 | 17 |
| 2006 | 14 | 12 |
| 2007 | 10 | 17 |
| 2008 | 24 | 22 |
| 2009 | 29 | 19 |
| 2010 | 22 | 16 |
| 2011 | 24 | 16 |
| 2012 | 25 | 29 |
| 2013 | 33 | 23 |
| 2014 | 41 | 28 |
| 2015 | 39 | 30 |
| 2016 | 47 | 28 |
| 2017 | 47 | 54 |
| 2018 | 48 | 55 |
| 2019 | 81 | 61 |
| 2020 | 71 | 42 |
| 2021 | 72 | 53 |
| 2022 | 49 | 63 |
| 2023 | 64 | 43 |
| 2024 | 28 | 43 |
| 2025 | 46 | 25 |
| 2026 | 26 | 17 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Compiling a tensor tiling specification to multi-dimensional data mover circuit configurations6 Oct 2026US 12,755,077 B2Xilinx, Inc.
- Seamless universal verification methodology1 Sep 2026US 12,724,070 B1Amazon Technologies, Inc.
- Systems and methods for memory randomization18 Aug 2026US 12,711,283 B1Cadence Design Systems, Inc.
- Hybrid switching architecture for SerDes communication channels in reconfigurable hardware modeling circuits28 Jul 2026US 12,694,178 B2Siemens Industry Software Inc.
- Systems and methods for programmable fabric design compilation28 Jul 2026US 12,694,180 B2Altera Corporation
- Processor controlled programmable logic device modification1 Oct 2026US 2026/0299908 A1Altera Corporation
- Integrated routing assembly and system using same17 Sep 2026US 2026/0278238 A1Molex Incorporated
- Circuit Implementation on Processing Circuitry10 Sep 2026US 2026/0268052 A1Altera Corporation
- Systems and methods for hardware acceleration of masking and normalizing data with a triangular input mask20 Aug 2026US 2026/0244836 A1Microsoft Technology Licensing, LLC
- Memory mapping for memory, memory modules, and non-volatile memory13 Aug 2026US 2026/0236257 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Multiprocessor for hardware emulation483US 5,551,013 AInternational Business Machines Corporation · 1996
- Method of using electronically reconfigurable logic circuits320US 5,036,473 AMentor Graphics Corporation · 1991
- Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system311US 5,452,239 AQuickturn Design Systems, Inc. · 1995
- Work group computing for electronic design automation309US 5,983,277 AAltera Corporation · 1999
- Virtual interconnections for reconfigurable logic systems303US 5,761,484 AMassachusetts Institute of Technology · 1998