G06F 13/1631
Through address comparison
Official title: {through address comparison}
G06F13/1631 (Through address comparison) appears on 226 US grants and 175 published applications in this corpus.
Search patents in G06F- Granted patents
- 226
- Published applications
- 175
- Assignees
- 114
- Inventors
- 541
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 2 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 3 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 1 | 0 |
| 1995 | 3 | 0 |
| 1996 | 4 | 0 |
| 1997 | 4 | 0 |
| 1998 | 8 | 0 |
| 1999 | 11 | 0 |
| 2000 | 8 | 0 |
| 2001 | 9 | 3 |
| 2002 | 11 | 4 |
| 2003 | 11 | 7 |
| 2004 | 4 | 6 |
| 2005 | 4 | 15 |
| 2006 | 10 | 11 |
| 2007 | 6 | 9 |
| 2008 | 6 | 9 |
| 2009 | 8 | 4 |
| 2010 | 3 | 4 |
| 2011 | 4 | 2 |
| 2012 | 3 | 3 |
| 2013 | 2 | 3 |
| 2014 | 4 | 8 |
| 2015 | 9 | 3 |
| 2016 | 5 | 5 |
| 2017 | 4 | 3 |
| 2018 | 3 | 5 |
| 2019 | 9 | 10 |
| 2020 | 5 | 6 |
| 2021 | 5 | 6 |
| 2022 | 11 | 14 |
| 2023 | 10 | 9 |
| 2024 | 8 | 13 |
| 2025 | 10 | 7 |
| 2026 | 8 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Systems and methods for load balancing memory traffic25 Aug 2026US 12,717,733 B2Altera Corporation
- Reordering memory controller4 Aug 2026US 12,699,531 B2Rambus Inc.
- On-chip interconnect for memory channel controllers14 Apr 2026US 12,602,334 B2Google Inc.
- Scalable network-on-chip for high-bandwidth memory10 Mar 2026US 12,572,500 B2Altera Corporation
- Methods, apparatus, and articles of manufacture to determine memory access integrity based on feedback from memory17 Feb 2026US 12,554,579 B2Texas Instruments Incorporated
- Scalable Network-on-Chip for High-Bandwidth Memory17 Sep 2026US 2026/0277851 A1Altera Corporation
- Request coalescing method, unit, and chip3 Sep 2026US 2026/0259836 A1Verisilicon Microelectronics (Chengdu) Co., Ltd.
- Techniques for efficiently handling misaligned sequential reads9 Jul 2026US 2026/0195072 A1Micron Technology, Inc.
- Cxl device and system25 Jun 2026US 2026/0178517 A1Samsung Electronics Co., Ltd.
- Memory access control circuitry11 Jun 2026US 2026/0161575 A1Arm Limited
Most cited
By later US patents
- Multi-processor DRAM controller that prioritizes row-miss requests to stale banks131US 5,745,913 AExponential Technology, Inc. · 1998
- System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory124US 5,459,842 AInternational Business Machines Corporation · 1995
- High-throughput interconnect allowing bus transactions based on partial access requests98US 5,911,051 AIntel Corporation · 1999
- Method and apparatus for a high-speed memory subsystem95US 6,526,471 B1Digeo, Inc. · 2003
- Memory access buffer and reordering apparatus using priorities92US 6,145,065 AMatsushita Electric Industrial Co., Ltd. · 2000