Method and apparatus for a high-speed memory subsystem

A memory controller for responding to a memory access request to a synchronous dynamic random access memory (SDRAM) from a processor, said memory controller comprising:

• an address buffer, said address buffer for latching a memory address of said memory access request;
• at least one memory row register, said memory row register for storing a memory row address of an active row in an associated memory bank of said SDRAM, said SDRAM directly connected to a processor bus;
• and
• memory control logic, said memory control logic determining if said memory address of said memory access request is within an active row of said SDRAM and responding to a memory access within a single clock cycle if said memory address of said memory access request is within said active row of said SDRAM, else said memory control logic signaling to said processor that said memory controller is not ready if said memory address of said memory access request is within an inactive row.

A computer system, said computer system comprising:

• a processor, said processor having a processor bus, said processor bus comprising address lines, data lines, and control lines;
• a synchronous dynamic random access memory (SDRAM), said SDRAM directly coupled to address and data lines of said processor bus;
• a memory controller coupled to said address lines and control lines, said memory controller comprising:
• at least one memory row register, said memory row register for storing a memory row address of an active row in an associated memory bank of said SDRAM;
• and
• memory control logic, said memory control logic determining if said memory address of a memory access request is within an active row of said SDRAM and initiating a memory access to said SDRAM within a single clock cycle if said memory access request is within an active row of said SDRAM.

A method for responding to a memory access request from a processor comprising:

• means for latching a memory write address for said memory write request from a processor into an address buffer of said memory controller while simultaneously determining if a memory row of said SDRAM encompassing said memory write address is active using logic in said memory controller, said SDRAM directly coupled to a processor bus;
• means for accepting data into a memory location of said SDRAM associated with said memory write address without delay when a memory row containing said memory location associated with said memory write address is active;
• and
• means for signaling from said memory controller to said processor that said memory controller is not ready to accept data when said memory row containing said memory location of said SDRAM associated with said memory write address is not active.