US 6,145,065 A · Memory access buffer and reordering apparatus using priorities

Abstract

A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.

Claims10

Dependent claims

A multiple address holding memory apparatus which is shared by a plurality of processes or a plurality of processors and which transfers data with said plurality of processes or said plurality of processors, said apparatus comprising:

a main memory part having an address input terminal;
an address bus for inputting addresses which are used for accessing said main memory part from said plurality of processes or said plurality of processors in accordance with a first order, and for inputting control signals which control said main memory part;
a data bus for transferring data between said plurality of processes or said plurality of processors and said main memory part;
an address temporary part which is disposed at said address input terminal of said main memory part, said address temporary memory part holding a plurality of addresses which are inputted through said address bus and a plurality of control signals which correspond to said plurality of addresses, and said address temporary memory part supplying said addresses which are held therein to said main memory part while supplying said control signals to said main memory part;
and
a permutation part which permutes said plurality of addresses held in said address temporary memory part into a second order which realizes high-speed accessing of said main memory part regardless of said first order in which addresses are input in said address temporary memory part for accessing said main memory part, said address temporary memory part supplying said addresses and said control signals to said main memory part sequentially in accordance with said second order, wherein said second order gives higher priority to permutation in accordance with priority ranks of accesses than to permutation in accordance with an order which realizes high-speed accessing.

3 more elements

a main memory part having an address input terminal;
an address bus for inputting addresses which are used for accessing said main memory part from said plurality of processes or said plurality of processors in accordance with a first order, and for inputting control signals which control said main memory part;
a data bus for transferring data between said plurality of processes or said plurality of processors and said main memory part;
an address temporary memory part which is disposed at said address input terminal of said main memory part, said address temporary memory part holding a plurality of addresses which are inputted through said address bus and a plurality of control signals which correspond to said plurality of addresses, and said address temporary memory part supplying said addresses which are held therein to said main memory part while supplying said control signals to said main memory part;
and
a permutation part which permutes said plurality of addresses held in said address temporary memory part into a second order which realizes high-speed accessing of said main memory part regardless of said first order in which addresses are input in said address temporary memory part for accessing said main memory part, said address temporary memory part supplying said addresses and said control signals to said main memory part in accordance with said second order,
wherein said address temporary memory part includes:
temporary memory means for temporarily storing addresses for accessing said main memory part and control signals;
a priority order deciding part for deciding priority ranks of said plurality of processes or said plurality of processors, accepting said addresses for accessing said main memory part and said control signals in the order of said priority ranks, and outputting a decision request signal upon acceptance of said addresses for accessing said main memory part and said control signals;
an empty address search part for searching for empty addresses in said temporary memory means in response to said decision request signal, said empty addresses being for temporarily storing said addresses for accessing said main memory part and said control signals;
an input address generation part for supplying said empty addresses found in said temporary memory means to said temporary memory mens as input addresses for writing data, based on a result of search which is performed by said empty address search part;
and
a control signal timing generation part for supplying an output signal from said temporary memory means to said main memory part at proper timing for accessing said main memory part, and
said permutation part includes:
an order deciding part for deciding an order of addresses in said temporary memory means based on information of said addresses and said control signals which are stored at the respective addresses in said temporary memory means;
a stored order replacing part for storing an order which is decided by said order deciding part;
and
an output address generation part for providing said temporary memory means with output addresses for reading data, in accordance with contents which are stored in said stored order replacing part.

15 more elements

A multiple address holding memory which is shared by a plurality of processes or a plurality of processors and which transfers data with said plurality of processes or said plurality of processors, said apparatus comprising:

a main memory part having an address input terminal;
an address bus for inputting addresses which are used for accessing said main memory part from said plurality of processes or said plurality of processors in accordance with a first order, and for inputting control signals which control said main memory part;
a data bus for transferring data between said plurality of processes or said plurality of processors and said main memory part;
an address temporary memory part which is disposed at said address input terminal of said main memory part, said address temporary memory part holding a plurality of addresses which are inputted through said address bus and a plurality of control signals which correspond to said plurality of addresses, and said address temporary memory part supplying said addresses which are held therein to said main memory part while supplying said control signals to said main memory part;
and
a permutation part which permutes said plurality of addresses held in said address temporary memory part into a second order which realizes high-speed accessing of said main memory part regardless of said first order in which addresses are input in said address temporary memory part for accessing said main memory part, said address temporary memory part supplying said addresses and said control signals to said main memory part in accordance with said second order, wherein
said second order gives higher priority to permutation in accordance with priority ranks of accesses than to permutation in accordance with an order which realizes high-speed accessing, wherein
said address temporary memory part includes:
temporary memory means for temporarily storing addresses for accessing said main memory part and control signals;
a priority order deciding part for deciding priority ranks of said plurality of processes or said plurality of processors, accepting said addresses for accessing said main memory part and said control signals in the order of said priority ranks, and outputting a decision request signal upon acceptance of said addresses for accessing said main memory part and said control signals;
an empty address search part for searching for empty addresses in said temporary memory means in response to said decision request signal, said empty addresses being for temporarily storing said addresses for accessing said main memory part and said control signals;
an input address generation part for supplying said empty addresses found in said temporary memory means to said temporary memory means as input addresses for writing data, based on a result of search which is performed by said empty address search part;
and
a control signal timing generation part for supplying an output signal from said temporary memory means to said main memory part at proper timing for accessing said main memory part, and
said permutation part includes:
an order deciding part for deciding an order of addresses in said temporary memory means based on information of said addresses and said control signals which are stored at the respective addresses in said temporary memory means;
a stored order replacing part for storing an order which is decided by said order deciding part;
and
an output address generation part for providing said temporary memory means with output addresses for reading data, in accordance with contents which are stored in said stored order replacing part.

16 more elements

Dependencies are inferred from the claim text.

Memory access buffer and reordering apparatus using priorities

Life of this patent

Memory access buffer and reordering apparatus using priorities

Life of this patent

Abstract

Claims10