G06F 13/161
With latency improvement
Official title: {with latency improvement}
G06F13/161 (With latency improvement) appears on 1,944 US grants and 1,854 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,944
- Published applications
- 1,854
- Assignees
- 386
- Inventors
- 3,281
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 2 | 0 |
| 1980 | 3 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 2 | 0 |
| 1986 | 3 | 0 |
| 1987 | 4 | 0 |
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 3 | 0 |
| 1992 | 3 | 0 |
| 1993 | 4 | 0 |
| 1994 | 6 | 0 |
| 1995 | 11 | 0 |
| 1996 | 10 | 0 |
| 1997 | 19 | 0 |
| 1998 | 38 | 0 |
| 1999 | 38 | 0 |
| 2000 | 38 | 0 |
| 2001 | 54 | 12 |
| 2002 | 47 | 57 |
| 2003 | 61 | 52 |
| 2004 | 51 | 48 |
| 2005 | 45 | 63 |
| 2006 | 37 | 48 |
| 2007 | 32 | 50 |
| 2008 | 41 | 48 |
| 2009 | 46 | 31 |
| 2010 | 27 | 36 |
| 2011 | 34 | 44 |
| 2012 | 45 | 47 |
| 2013 | 37 | 48 |
| 2014 | 53 | 100 |
| 2015 | 84 | 78 |
| 2016 | 78 | 75 |
| 2017 | 102 | 88 |
| 2018 | 79 | 148 |
| 2019 | 131 | 107 |
| 2020 | 105 | 80 |
| 2021 | 82 | 79 |
| 2022 | 86 | 121 |
| 2023 | 91 | 91 |
| 2024 | 113 | 124 |
| 2025 | 109 | 107 |
| 2026 | 73 | 72 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- I/O management using page-level aging6 Oct 2026US 12,754,859 B1Dell Products L. P.
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Method and apparatus for encoding and multiplexing a stream in a serial channel6 Oct 2026US 12,756,749 B2NXP USA, Inc.
- Dynamic memory power capping with criticality awareness29 Sep 2026US 12,748,620 B2Advanced Micro Devices, Inc.
- Method for configuring memory placement in a computing device29 Sep 2026US 12,748,690 B2Harman International Industries, Incorporated
- Information processing device, information processing system, and information processing method1 Oct 2026US 2026/0300191 A1Hitachi, Ltd.
- Data Transfer Device for Heterogeneous Memory Systems1 Oct 2026US 2026/0300192 A1Advanced Micro Devices, Inc.
- Memory system24 Sep 2026US 2026/0288631 A1Kioxia Corporation
- System and method for low latency packet processing24 Sep 2026US 2026/0288657 A1Mellanox Technologies, Ltd.
- Virtualized parallel access architecture for flash memory17 Sep 2026US 2026/0277829 A1Silicon Motion, Inc.
Most cited
By later US patents
- Apparatus for synchronously generating clock signals in a data processing system430US 5,243,703 ARambus Inc. · 1993
- Scheduling policy for queues in a non-volatile solid-state storage376US 8,874,836 B1Pure Storage, Inc. · 2014
- Integrated circuit I/O using high performance bus interface325US 5,319,755 ARambus Inc. · 1994
- Memory circuitry having bus interface for receiving information in packets and access time registers282US 5,606,717 ARambus Inc. · 1997
- Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory275US 5,737,748 ATexas Instruments Incorporated · 1998