G06F 13/1626
By reordering requests
Official title: {by reordering requests}
G06F13/1626 (By reordering requests) appears on 648 US grants and 622 published applications in this corpus.
Search patents in G06F- Granted patents
- 648
- Published applications
- 622
- Assignees
- 192
- Inventors
- 1,326
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 2 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 3 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 1 | 0 |
| 1995 | 3 | 0 |
| 1996 | 4 | 0 |
| 1997 | 5 | 0 |
| 1998 | 8 | 0 |
| 1999 | 17 | 0 |
| 2000 | 8 | 0 |
| 2001 | 17 | 3 |
| 2002 | 16 | 11 |
| 2003 | 22 | 19 |
| 2004 | 13 | 22 |
| 2005 | 16 | 24 |
| 2006 | 19 | 23 |
| 2007 | 12 | 17 |
| 2008 | 16 | 16 |
| 2009 | 18 | 9 |
| 2010 | 11 | 14 |
| 2011 | 9 | 10 |
| 2012 | 16 | 24 |
| 2013 | 15 | 20 |
| 2014 | 16 | 36 |
| 2015 | 34 | 23 |
| 2016 | 28 | 23 |
| 2017 | 29 | 14 |
| 2018 | 17 | 29 |
| 2019 | 34 | 30 |
| 2020 | 24 | 21 |
| 2021 | 18 | 24 |
| 2022 | 30 | 55 |
| 2023 | 34 | 31 |
| 2024 | 41 | 51 |
| 2025 | 46 | 46 |
| 2026 | 35 | 27 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Dynamic memory power capping with criticality awareness29 Sep 2026US 12,748,620 B2Advanced Micro Devices, Inc.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Efficient input/output memory management unit8 Sep 2026US 12,730,757 B2Advanced Micro Devices, Inc.
- Data Transfer Device for Heterogeneous Memory Systems1 Oct 2026US 2026/0300192 A1Advanced Micro Devices, Inc.
- Scalable Network-on-Chip for High-Bandwidth Memory17 Sep 2026US 2026/0277851 A1Altera Corporation
- Request coalescing method, unit, and chip3 Sep 2026US 2026/0259836 A1Verisilicon Microelectronics (Chengdu) Co., Ltd.
- Asymmetric partial link width state management6 Aug 2026US 2026/0228139 A1
- Dynamic memory power capping with criticality awareness30 Jul 2026US 2026/0219926 A1Advanced Micro Devices, Inc.
Most cited
By later US patents
- Scheduling policy for queues in a non-volatile solid-state storage376US 8,874,836 B1Pure Storage, Inc. · 2014
- Multi-processor DRAM controller that prioritizes row-miss requests to stale banks131US 5,745,913 AExponential Technology, Inc. · 1998
- System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory124US 5,459,842 AInternational Business Machines Corporation · 1995
- Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus116US 6,526,484 B1Infineon Technologies AG · 2003
- Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution99US 6,216,178 B1Infineon Technologies AG · 2001