Efficient input/output memory management unit
AssigneeAdvanced Micro Devices, Inc.
InventorWei Sheng
Life of this patent
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Abstract
An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the valid bit.
Claims21
An input/output memory management unit, comprising:
- a control logic circuit for providing physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices;
- and
- a device table entry valid bit array for storing a plurality of valid bits corresponding to different ones of said plurality of input/output devices,
- wherein said control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the first valid bit, and
- wherein the input/output memory management unit is implemented as an integrated circuit.
A data processing system comprising:
- a plurality of input/output devices, each generating memory access requests for a system memory;
- an input/output memory management unit that translates virtual addresses of the memory access requests into physical addresses;
- a data fabric for selectively routing the physical addresses to a plurality of ports thereof;
- and
- a memory controller having a first port coupled to a first downstream port of the data fabric, and a second port adapted to be coupled to the system memory,
- wherein the input/output memory management unit comprises a device table entry valid bit array for storing a plurality of valid bits corresponding to different ones of said plurality of input/output devices,
- wherein said input/output memory management unit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in the system memory in response to a state of the first valid bit and,
- wherein the input/output memory management unit is implemented as an integrated circuit.
A method of input/output device memory management, comprising:
- receiving a virtual address from a first input/output device, and in response to receiving the virtual address:
- checking a first valid bit corresponding to the first input/output device in a device table entry valid bit array in an input/output memory management unit, wherein the input/output memory management unit is implemented as an integrated circuit;
- when the first valid bit has a first state, providing a physical address to a system memory without translating the virtual address;
- and
- when the first valid bit has a second state, accessing a device table entry of a device table in the system memory, and translating the virtual address to the physical address according to information in the device table entry.
Dependencies are inferred from the claim text.