System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory

In a personal computer having a memory for storing information at a plurality of addressable locations, each location including at least four bytes of information, a memory controller connected to said memory for controlling operation thereof, a memory controller bus connected to said memory controller, a local bus including a local address bus, a local control bus, and a local data bus having a width of at least four bytes for transferring from one to four bytes of information on each write cycle, and a processor connected to said local bus, said processor being operative to initiate first and second partial write cycle requests on consecutive local bus cycles, said first partial write cycle request specifying first data to be written in said memory at a first address, said second partial write cycle request specifying second data to be written in said memory at said first address, said first data having one or two bytes and said second data having one or two bytes, said processor asserting on said local address bus in each partial write request byte enable signals defining each byte being transferred, the improvement comprising:

• a. a partial write cycle compression write buffer connected to said local bus and said memory controller bus, comprising
• first buffer means connected to said local bus and comprising:
• i. first data buffer connected to said local data bus for selectively receiving and buffering said first data in response to a LATCH signal, and for merging said second data with said first data buffer in said first data buffer, in response to a COMP BUFF control signal,
• ii. a first address buffer connected to said local address bus for storing said first address for selectively receiving and buffering said first memory address and said byte enable signals;
• a comparator connected to said local address bus and to said first address buffer and being operative to compare the address buffer in said first address buffer with the address on said local bus in said second partial write cycle request and generating a MATCH signal when the two addresses being compared are the same;
• a control logic connected to said first buffer means, to said local bus, and to said memory controller bus, said control logic being operable to
• i. generate said LATCH signal in response to said first partial write request,
• ii. generate said COMP buff signal in response to said MATCH signal,
• iii. transmit to said processor acknowledgment signals after data from each request has been stored in said first data buffer, which acknowledgement signals indicate to said processor that each of said first and second requests has been completed, before said first data and said second data have been written into said memory, and
• iv. compress said first and said second partial write cycles into a single memory controller bus write cycle for simultaneously writing said first and second data in said memory;
• b. said memory controller operates said memory during a partial write cycle and perform a read-modify-write operation, and said memory controller is operative to modify data read from said memory and write said first data and said second data into said memory;
• c. said processor is operative to assert a third write request on said local bus before completion of said single memory controller write bus cycle, said third write request being to write data into said memory at a second address different than said first address, said computer further comprising:
• second buffer means connected to said local bus in parallel with said first buffer means, said second buffer means being selectively operable to receive and buffer data and address from said third write request pending completion of said single memory controller write bus cycle.