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US 2026/0277851 A1Published application
Scalable Network-on-Chip for High-Bandwidth Memory
AssigneeAltera Corporation
InventorsChee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
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Abstract
Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
Claims1
An electronic device, comprising:
- a high-bandwidth memory (HBM) device;
- and
- an integrated circuit device coupled to the HBM device, the integrated circuit device comprising:
- a memory controller communicatively coupled to the HBM device and configurable to receive data from the HBM device;
- and
- a first Network-on-Chip (NOC) coupled to the memory controller and configurable to receive the data from the memory controller, wherein the first NOC comprises a first router comprising a set of ports and crossbar circuitry configurable to link ports of the set of ports.
3 more elements
Dependencies are inferred from the claim text.