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US 12,572,500 B2Granted
Scalable network-on-chip for high-bandwidth memory
AssigneeAltera Corporation
InventorsChee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
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Abstract
Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
Claims20
An electronic device, comprising:
- a high-bandwidth memory (HBM) device;
- and
- an integrated circuit device coupled to the HBM device, the integrated circuit device comprising:
- a memory controller communicatively coupled to the HBM device and configurable to receive data from the HBM device;
- a memory controller Network-on-Chip (NOC) coupled to the memory controller and configurable to receive the data from the memory controller;
- a fabric NOC;
- and
- a plurality of processing cores, wherein a first data processing core of the plurality of processor cores is configurable to access the memory controller through the fabric NOC and a second data processing core of the plurality of processing cores is configurable to access the memory controller through a direct interconnect coupled to a first router of the fabric NOC.
5 more elements
An integrated circuit device, comprising:
- a plurality of processing cores;
- a memory controller communicatively coupled to a high bandwidth memory (HBM) device and configured to receive data from the HBM device;
- a first memory controller Network-on-Chip (NOC) configurable to communicatively couple the integrated circuit device to the HBM device, wherein the first memory controller NOC comprises a first plurality of routers in a horizontal configuration;
- and
- a second fabric NOC coupled to the plurality of processing cores and comprising a second plurality of routers in a vertical configuration, wherein the second fabric NOC is configurable to:
- receive data from a first router of the first memory controller NOC through a second router of the second fabric NOC;
- and
- transfer the data to a processing core of the plurality of processing cores,
- wherein a first data processing core of the plurality of processing cores is to access the memory controller through the second fabric NOC, and
- wherein a second data processing core of the plurality of processing cores is to access the memory controller through a direct interconnect coupled to a third router of the fabric second NOC.
7 more elements
An electronic device comprising:
- a high-bandwidth memory (HBM) device;
- and
- an integrated circuit device coupled to the HBM device, the integrated circuit device comprising:
- a plurality of data processing cores;
- a memory controller communicatively coupled to the HBM device and configured to receive data from the HBM device;
- a first Network-on-Chip (NOC) configurable to communicatively couple the integrated circuit device to the HBM device;
- and
- a second NOC coupled to the first NOC and configurable to receive a data packet from the first NOC and route the data packet to one or more of the plurality of data processing cores, wherein a first router of the second NOC is configurable to receive the data packet from a second router of the first NOC and transfer the data to a third router of the second NOC based on a destination address of the data packet.
5 more elements
Dependencies are inferred from the claim text.