High-throughput interconnect allowing bus transactions based on partial access requests

A method of performing a bus transaction, the bus transaction including a data transfer and an access request for requesting the data transfer, the method comprising:

• separating the access request into a plurality of subsets, the plurality of subsets including a first subset and a second subset;
• determining whether the second subset is different from a corresponding second subset of a previous access request;
• transmitting the first subset to a target device to initiate the bus transaction;
• and
• transmitting the second subset to the target device only if the second subset is different from the corresponding second subset of the previous access request.

A method of performing a bus transaction, the bus transaction including an access request for requesting a data transfer, the method comprising:

• separating the access request into a plurality of subsets, the plurality of subsets including a first subset and a second subset;
• using only the first subset of the access request to initiate the bus transaction;
• and
• providing the second subset of the access request to a target device only to update state in the target device.

A device operable as a bus master in a processing system, the device comprising:

• means for transmitting a first subset of an access request to a target device on a first set of signal lines, the access request for requesting a transfer of data;
• means for determining whether a second subset of the access request is different from a corresponding second subset of a previous access request;
• means for transmitting the second subset of the access request to the target device on the first set of signal lines only if the second subset is different from the corresponding second subset of the previous access request;
• and
• means for transferring the data on a second set of signal lines.

A device operable to perform transactions on a bus in a processing system, the bus including a set of address/data lines, the device comprising:

• first logic coupled to the address/data lines and configured to transmit addresses of a first transfer mode to a target device on the address/data lines and to communicate data corresponding to the addresses of the first transfer mode with the target device on the address/data lines;
• second logic coupled to a set of sideband address lines and configured to transmit addresses of a second transfer mode to a target device on the sideband address lines, wherein data corresponding to the addresses of the second transfer mode are communicated with the target device on the address/data lines, the second logic including:
• means for transmitting a first subset of an address of the second transfer mode to a target device on the sideband address lines;
• means for determining whether a second subset of the address of the second transfer mode differs from a corresponding second subset of a previous address;
• and
• means for transmitting the second subset to the target device on the sideband address lines only if the second subset differs from the corresponding second subset of the previous address.

A processing system comprising:

• a processor;
• a memory coupled to the processor;
• a bus coupled to the processor and the memory;
• and
• a device coupled to the bus and operable as a bus master, wherein the device is configured to:
• transmit a first subset of an access request to a target device, the access request for requesting a transfer of data on the bus;
• transmit a second subset of the access request to the target device only if the second subset is different from a corresponding second subset of a previous access request;
• and
• communicate the data with the target device on the bus in response to transmitting the first subset and not the second subset of the access request to the target device.

A computer system comprising:

• a processor;
• a memory controller coupled to the processor;
• a memory coupled to the memory controller;
• a bus coupled to the memory controller, the bus including a set of address/data lines;
• a device coupled to the bus and operable as a bus master to transmit memory access requests to the memory controller, the device further coupled to the memory controller by a set of sideband address lines, the device including:
• first logic coupled to the address/data lines and configured to transmit access requests of a first transfer mode onto the address/data lines and to communicate data corresponding to the access requests of the first transfer mode on the address/data lines;
• second logic coupled to the sideband address lines and configured to transmit access requests of a second transfer mode on the sideband address lines, wherein data corresponding to the access requests of the second transfer mode are communicated on the address/data lines, the second logic including:
• means for transmitting a first subset of an access request of the second transfer mode on the sideband address lines;
• means for determining whether a second subset of the access request of the second transfer mode differs from a corresponding second subset of a previous access request;
• and
• means for transmitting the second subset on the sideband address lines as part of the access request of the second mode only if the second subset differs from the corresponding second subset of the previous access request.