On-chip interconnect for memory channel controllers
AssigneeGoogle Inc.
InventorsRahul Nagarajan, Hema Hariharan
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Abstract
Methods, systems, and apparatus, including computer-readable media, are described for an integrated circuit that accelerates machine-learning computations. The circuit includes processor cores that each include multiple channel controllers; an interface controller for coupling each channel controller to any memory channel of a system memory; and a fetch unit in each channel controller. Each fetch is configured to: receive channel data that encodes addressing information; obtain, based on the addressing information, data from any memory channel of the system memory using the interface controller; and write the obtained data to a vector memory of the processor core via the corresponding channel controller that includes the respective fetch unit.
Claims20
An integrated circuit used to accelerate machine-learning computations, the integrated circuit comprising:
- an interface controller configured to dynamically couple a channel controller to different memory channels of a memory unit;
- and
- a fetch unit of the channel controller, the fetch unit being configured to:
- i) receive a request;
- ii) fetch, based on the request, data from any of the different memory channels of the memory unit based on a control signal generated by the interface controller;
- and
- iii) write, to a vector memory of the integrated circuit, the data fetched from any of the different memory channels of the memory unit.
A method for accelerating machine-learning computations executed using an integrated circuit, the method comprising:
- receiving a request for data used to execute the machine-learning computations;
- based on the request and using an interface controller of the integrated circuit, dynamically coupling a channel controller of the integrated circuit to different memory channels of a memory unit that stores the data;
- in response to dynamically coupling, fetching, using a fetch unit of the channel controller, data from any of the different memory channels of the memory unit based on a control signal generated by the interface controller;
- and
- writing, to a vector memory of the integrated circuit, the data fetched from any of the different memory channels of the memory unit.
Dependencies are inferred from the claim text.