Systems and methods for load balancing memory traffic

A circuit system comprising:

• first and second memory devices;
• first and second memory controller circuits;
• first and second logic blocks;
• and
• a load balancing multiplexer circuit that provides a first read operation issued by the first logic block to the second memory controller circuit for transmission to the second memory device based on a first indication that the second logic block is idle and not issuing second read operations through the second memory controller circuit, wherein the first indication further indicates that the second memory controller circuit has first available memory bandwidth,
• wherein the first memory controller circuit transmits a third read operation issued by the first logic block to the first memory device, wherein the second memory controller circuit transmits the first read operation to the second memory device, and
• wherein the first and the second logic blocks, the first and the second memory controller circuits, and the load balancing multiplexer circuit are in an integrated circuit.