G01R 31/2815
Functional tests
Official title: {Functional tests, e.g. boundary scans, using the normal I/O contacts (contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00)}
G01R31/2815 (Functional tests) appears on 157 US grants and 136 published applications in this corpus.
Search patents in G01R- Granted patents
- 157
- Published applications
- 136
- Assignees
- 111
- Inventors
- 292
- Latest grant
- 9 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 3 | 0 |
| 1997 | 8 | 0 |
| 1998 | 3 | 0 |
| 1999 | 3 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 1 |
| 2002 | 2 | 2 |
| 2003 | 3 | 1 |
| 2004 | 4 | 4 |
| 2005 | 3 | 6 |
| 2006 | 3 | 12 |
| 2007 | 7 | 3 |
| 2008 | 5 | 7 |
| 2009 | 6 | 5 |
| 2010 | 7 | 3 |
| 2011 | 10 | 12 |
| 2012 | 2 | 4 |
| 2013 | 5 | 2 |
| 2014 | 8 | 4 |
| 2015 | 4 | 7 |
| 2016 | 4 | 3 |
| 2017 | 5 | 3 |
| 2018 | 5 | 9 |
| 2019 | 9 | 6 |
| 2020 | 5 | 6 |
| 2021 | 8 | 10 |
| 2022 | 6 | 7 |
| 2023 | 10 | 9 |
| 2024 | 5 | 2 |
| 2025 | 6 | 6 |
| 2026 | 2 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Interface to full and reduced pin JTAG devices9 Jun 2026US 12,650,466 B2Texas Instruments Incorporated
- Universal socket test card5 May 2026US 12,618,894 B2Hewlett Packard Enterprise Development LP
- Directional control of scan capture through shared wrapper cells14 Oct 2025US 12,442,859 B1Google Inc.
- Circuit board and monitoring method therefor23 Sep 2025US 12,422,467 B2Wiwynn Corporation
- Semiconductor package9 Sep 2025US 12,412,876 B2Panasonic Automotive Systems Co., Ltd.
- Segmented testing method for functional safety testing circuit, electronic device, and storage medium18 Jun 2026US 2026/0169060 A1VeriSilicon Microelectronics (Shanghai) Co., Ltd.
- Electronic component test method optimized by a learning algorithm26 Feb 2026US 2026/0056248 A1Bealach Na Bo Finne Teoranta
- Method and apparatus for circuit board detection, computer device, storage medium, and program products16 Oct 2025US 2025/0321262 A1
- Wiring board and mounting structure21 Aug 2025US 2025/0267792 A1KYOCERA Corporation
- Methods for Verifying Integrity and Authenticity of a Printed Circuit Board5 Jun 2025US 2025/0180628 A1
Most cited
By later US patents
- Addressable shadow port and protocol for serial bus networks133US 5,483,518 ATexas Instruments Incorporated · 1996
- Boundary scan architecture analog extension with direct connections103US 5,887,001 ABull HN Information Systems Inc. · 1999
- Scan-based delay tests having enhanced test vector pattern generation63US 5,642,362 AInternational Business Machines Corporation · 1997
- Reduced power apparatus and method for testing high speed components62US 5,614,838 AInternational Business Machines Corporation · 1997
- Scan interface chip (SIC) system and method for scan testing electronic systems52US 6,754,863 B1Silicon Graphics, Inc. · 2004