Scan-based delay tests having enhanced test vector pattern generation

An integrated circuit comprising at least one block of logic having a plurality of input nodes and at least one output node, said integrated circuit further comprising:

• skewed-load delay fault test circuitry for testing said at least one block of logic, said skewed-load delay fault test circuitry being coupled to said plurality of input nodes for sequentially establishing at said plurality of input nodes at least a first multi-bit test vector for generating initialization logic states in said at least one block of logic and a second multi-bit test vector for provoking logical transitions at potential fault sites in said at least one block of logic, said skewed-load delay fault test circuitry including a scan-chain register and a plurality of XOR gates, wherein said plurality of XOR gates are organized as at least two sets of XOR gates, wherein XOR gates of the first set each have a first input coupled to an output of said scan-chain register, a second input coupled to a first control signal line, and an output coupled to one of said input nodes, wherein XOR gates of the second set each have a first input coupled to an output of said scan-chain register, a second input coupled to a second control signal line, and an output coupled to one of said input nodes, wherein for a first logic state appearing on said control signal lines a logic state of the output of the scan-chain register is coupled to said input nodes, and wherein for a second logic state appearing on said control signal lines an inverse of the logic state of the output of the scan-chain register is coupled to said input nodes, wherein said first inputs of said first set of XOR gates are coupled to non-adjacent stages of said scan-chain register, and wherein said first inputs of said second set of XOR gates are coupled to non-adjacent stages of said scan-chain register.

A multi-chip system comprised of a plurality of integrated circuits, wherein at least one of said integrated circuits comprises at least one block of logic having a plurality of input nodes and at least one output node, said multi-chip system further comprising:

• delay fault test circuitry internal to said at least one of said integrated circuits for testing said at least one block of logic,. said delay fault test circuitry being coupled to said plurality of input nodes for sequentially establishing at said plurality of input nodes at least a first multi-bit test vector for generating initialization logic states in said at least one block of logic and a second multi-bit test vector for provoking logical transitions at potential fault sites in said at least one block of logic, said delay fault test circuitry further being coupled to said at least one output node, said delay fault test circuitry comprising a scan-chain register and a plurality of XOR gates, wherein said plurality of XOR gates are organized as at least two sets of XOR gates, wherein XOR gates of the first set each have a first input coupled to an output of said scan-chain register, a second input coupled to an output of a first random bit source, and an output coupled to one of said input nodes, wherein XOR gates of the second set each have a first input coupled to an output of said scan-chain register, a second input coupled to an output of a second random bit source, and an output coupled to other ones of said input nodes;
• pseudorandom bit source means having an output coupled to a scan-in port of said scan-chain register;
• and
• signature register means coupled to a scan-out port of said scan-chain register.

An integrated circuit comprising at least one block of logic having a plurality of input nodes and a plurality of output nodes, said integrated circuit further comprising:

• broad-side delay fault test circuitry for testing said at least block of logic, said broad-side delay fault test circuitry being coupled to said plurality of input nodes for sequentially establishing at said plurality of input nodes at least a first multi-bit test vector for generating initialization logic states in said at least one block of logic and a second multi-bit test vector for provoking logical transitions at potential fault sites in said at least one block of logic, said broad-side delay fault test circuitry further being coupled to said plurality of output nodes, said broad-side delay fault test circuitry comprising,
• a multi-stage scan-chain register having a plurality of outputs individual ones of which are coupled to one of said input nodes;
• and
• a plurality of XOR gates each having a first input coupled to one of said plurality of output nodes, a second input coupled to an output of a source of random logic states, and an output coupled to a stage of said scan-chain register.

A method for performing a delay fault test so as to overcome a one-bit shift dependency of a second test vector upon a first test vector, comprising the steps of:

• loading the first test vector into a scan-chain register and applying outputs of the scan chain register to input nodes of a logic block under test, the step of applying including a step of generating initialization logic states within the logic block under test;
• performing a one bit shift of the first test vector to generate the second test vector;
• and
• modifying at least one bit of the second test vector by Exclusive-ORing the at least one bit with a test signal and applying the second test vector having the modified at least one bit to the input nodes of the logic block under test for provoking at least one logical transition at a potential fault site in the logic block under test.

A method for performing a broad-side delay fault test of at least one combinational logic block having a plurality of input nodes and a plurality of output nodes, the broad-side delay fault test being performed so as to overcome a skew in probability values appearing at the plurality of output nodes in response to an application of a first test vector to the plurality of input nodes, comprising the steps of:

• loading the first test vector into a scan-chain register and applying outputs of the scan chain register to the plurality of input nodes of the combinational logic block, the step of applying including a step of generating initialization logic states within the combinational logic block;
• outputting logic signals from the plurality of output nodes in response to the first test vector;
• Exclusive-ORing individual ones of the logic signals with a logic signal having a predetermined probability of being in a logic one or a logic zero state, thereby generating a second test vector having adjusted probability values;
• and
• coupling the second test vector to the input nodes of the combinational logic block for provoking logical transitions at potential fault sites in the combinational logic block.