Interface to full and reduced pin JTAG devices
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
Claims20
A debug interface circuit within a device, the debug interface circuit comprising:
- a first interface including a data input, a data output, a clock output and a control output;
- a second interface including a data input, a data output, a clock output, and a control output;
- a third interface including a clock output and a data input/output;
- and
- a control circuit operable to:
- receive a debug message from the first interface while the second interface is inactive;
- and
- output a first select signal to enable the first interface to operate the second interface or a second select signal to enable the first interface to operate the third interface.
An addressable debug interface circuit of a device, the addressable debug interface circuit comprising:
- a first interface operable to input a debug message including a start field, an address field, and a stop field;
- address circuitry operable to:
- compare the address field to an address of the addressable debug interface circuit;
- and
- in response to a match between the address field to the address of the addressable debug interface circuit, enable the addressable debug interface circuit to output data on the first interface;
- and
- command circuitry operable to enable, in response to the debug message, one of a plurality of second interfaces to input data from the first interface and output data to the first interface.
An addressable debug interface circuit of a device, the addressable debug interface circuit comprising:
- a clock input;
- a first interface coupled to the clock input and operable to input a debug message;
- first circuitry operable to enable the addressable debug interface circuit to output data on the first interface in response to the debug message;
- and
- second circuitry operable to enable the first interface to communicate with a second interface in response to the debug message.
Dependencies are inferred from the claim text.