Directional control of scan capture through shared wrapper cells

A system for an automatic test pattern generation partition test mode for testing a plurality of blocks and logic interfaces on a system-on-chip (SoC) comprising:

• a first block of an SOC;
• a first shared wrapper operably coupled with the first block, the first shared wrapper including a first input shared wrapper cell and a first output shared wrapper cell;
• and
• a first control circuit within the first block, the first control circuit comprising:
• a first NOT gate having an input and an output, the input coupled with a first sync interface test data register (TDR);
• a first OR gate having a first input, a second input, and an output, the first input coupled with the output of the first NOT gate and the second input coupled with a first scan enable pin;
• a first AND gate having a first input, a second input, and an output, the first input of the first AND gate coupled with a first in-test mode TDR and the second input of the first AND gate coupled with the output of the first OR gate;
• and
• a second AND gate having a first input, a second input, and an output, the first input of the second AND gate coupled with the output of the first OR gate and the second input of the second AND gate coupled with a first ex-test mode TDR.

A method for testing an integrated circuit (IC), the method comprising:

• receiving selection of a test mode for testing the IC;
• configuring logic of a shared wrapper cell to control a direction of a scan capture through the shared wrapper cell for the selected test mode;
• applying the scan capture for the selected test mode to the shared wrapper cell;
• and
• determining an output of the scan capture for the shared wrapper cell of the selected test mode;
• wherein the logic of the shared wrapper cell is configured using a control circuit, the control circuit comprising:
• a NOT gate, an input of the NOT gate being coupled to a sync interface test data register (TDR);
• an OR gate, a first input of the OR gate being coupled to an output of the NOT gate and a second input of the OR gate being coupled to a scan enable pin;
• a first AND gate, a first input of the first AND gate being coupled to an in-test mode TDR and
• a second input of the first AND gate being coupled to an output of the OR gate;
• and a second AND gate, a first input of the second AND gate being coupled to the output of the OR gate and a second input of the second AND gate being coupled to an ex-test mode TDR.