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US 6,754,863 B1Granted
Scan interface chip (SIC) system and method for scan testing electronic systems
AssigneeSilicon Graphics, Inc.
InventorLouis C. Grannis, III
Life of this patent
Estimating the term…
Abstract
A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.
Claims25
A scan test interface comprising:
- a scan test interface register for storing information related to scan test operations that support both partial reset operations and full reset operations;
- a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;
- a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register to support both a partial reset operation and full reset operation;
- a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain;
- a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain;
- and
- a reset circuit coupled to said scan test interface register, said reset circuit initiates a reset of said scan test interface register during a full reset operation, wherein said reset circuit comprises:
- a reset OR gate for issuing a reset signal when power is turned off or when a program scan interface (PSI) and test reset (TRSTN) signal are asserted;
- a voltage inverter coupled to said reset OR gate, said high logic voltage inverter outputs a logical one value momentarily when the power to said scan test interface is turned on and then outputs a logical zero value;
- a reset AND gate coupled to said reset OR gate, said reset AND gate outputs a logical one value when a program scan interface (PSI) signal and test reset (TRSTN) signal are asserted;
- and
- a test reset inverter coupled to said reset AND gate, said test reset inverter inverts said TRSTN signal.
9 more elements
A multi-drop scan interface chip (SIC) scan test system comprising:
- a plurality of downstream scannable devices arranged in a first separate scan test chains and a second separate scan test chain;
- a SIC coupled to said plurality of downstream scannable devices, said SIC supports both full reset and partial reset programming operations without requiring a full reset between programming operations;
- and
- a scan test system controller coupled to said SIC, said scan test system controller communicating said scan test signals to and from said SIC.
1 more element
A scan test interface comprising:
- a scan test interface register for storing information related to scan test operations;
- a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;
- a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;
- a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain and holds logic levels of subordinate scan test chain signals static when said scan test interface enters programming mode;
- and
- a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain.
3 more elements
A scan test interface method comprising the steps of:
- receiving scan test information from upstream scan test devices;
- transmitting scan test information to downstream devices;
- receiving scan test information from downstream devices;
- transmitting scan test information to upstream scan test devices;
- and
- facilitating flexible scan test operations including holding logic levels of subordinate scan test chain signals static when a scan test interface enters a programming mode.
3 more elements
Dependencies are inferred from the claim text.