Y10S 257/908
Dram configuration with transistors and capacitors of pairs of cells along a
Official title: Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines
Y10S257/908 (Dram configuration with transistors and capacitors of pairs of cells along a) appears on 218 US grants and 145 published applications in this corpus.
Search patents in Y10S- Granted patents
- 218
- Published applications
- 145
- Assignees
- 59
- Inventors
- 278
- Latest grant
- 9 Mar 2021
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 3 | 0 |
| 1994 | 2 | 0 |
| 1995 | 4 | 0 |
| 1996 | 4 | 0 |
| 1997 | 4 | 0 |
| 1998 | 7 | 0 |
| 1999 | 8 | 0 |
| 2000 | 12 | 0 |
| 2001 | 16 | 7 |
| 2002 | 21 | 25 |
| 2003 | 18 | 22 |
| 2004 | 21 | 16 |
| 2005 | 22 | 22 |
| 2006 | 13 | 12 |
| 2007 | 9 | 11 |
| 2008 | 8 | 10 |
| 2009 | 8 | 5 |
| 2010 | 13 | 4 |
| 2011 | 9 | 4 |
| 2012 | 5 | 2 |
| 2013 | 2 | 2 |
| 2014 | 4 | 1 |
| 2015 | 2 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 1 | 2 |
| 2021 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry9 Mar 2021US 10,943,907 B2Micron Technology, Inc.
- Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry7 Jul 2020US 10,707,211 B2Micron Technology, Inc.
- Semiconductor device including a thin film transistor and a capacitor30 Jun 2015US 9,070,773 B2Semiconductor Energy Laboratory Co.Ltd.
- Non-volatile semiconductor memory device and its manufacturing method3 Mar 2015US 8,969,942 B2Kabushiki Kaisha Toshiba
- Multi-resistive integrated circuit memory4 Nov 2014US 8,878,274 B2Micron Technology, Inc.
- Integrated Circuitry Comprising An Array, Method Of Forming An Array, Method Of Forming DRAM Circuitry, And Method Used In The Fabrication Of Integrated Circuitry20 Aug 2020US 2020/0266197 A1Micron Technology, Inc.
- Integrated Circuitry Comprising An Array, Method Of Forming An Array, Method Of Forming DRAM Circuitry, And Method Used In The Fabrication Of Integrated Circuitry26 Mar 2020US 2020/0098761 A1Micron Technology, Inc.
- Non-volatile semiconductor memory device and its manufacturing method3 Jul 2014US 2014/0183617 A1Kabushiki Kaisha Toshiba
- Semiconductor Device and Method for Preparing the Same6 Jun 2013US 2013/0140577 A1Semiconductor Energy Laboratory Co.Ltd.
- DRAM Layout with Vertical FETS and Method of Formation3 Jan 2013US 2013/0001663 A1Micron Technology, Inc.
Most cited
By later US patents
- Memory address decode array with vertical transistors127US 6,134,175 AMicron Technology, Inc. · 2000
- Methods for forming semiconductor structures105US 7,098,105 B2Micron Technology, Inc. · 2006
- Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array92US 6,034,389 AInternational Business Machines Corporation · 2000
- Trench MOSFET with structure having low gate charge89US 6,472,708 B1General Semiconductor, Inc. · 2002
- Semiconductor device having both memory and logic circuit and its manufacture89US 6,987,041 B2Fujitsu Limited · 2006