Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry

A method of forming DRAM circuitry, comprising:

• providing a substrate comprising pairs of recessed access devices, the recessed access devices individually comprising:
• a conductive gate in a trench in semiconductive in a semiconductive material;
• a gate insulator along sidewalls and a base of the trench between the conductive gate and the semiconductive material;
• a pair of source/drain regions in upper portions of the semiconductive material on opposing sides of the trench;
• a channel region in the semiconductive material below the pair of source/drain regions along the trench sidewalls and around the trench base;
• and
• one of the source/drain regions of the pair of source/drain regions in individual of the pairs of recessed access devices being laterally between two of the conductive gates of the pair of the recessed access devices and being shared by the individual pair of recessed access devices, the others of the source/drain regions of the pair of source/drain regions not being shared in the individual pair of recessed access devices;
• forming digitline structures that are individually directly electrically coupled to the shared source/drain region of multiple of the individual pairs of recessed access devices;
• forming conductive vias laterally between and spaced longitudinally along the digitline structures, the conductive vias comprising a first series of rows and a second series of rows, individual of the conductive vias comprising first and second opposing upper end-walls, the individual conductive vias being directly electrically coupled to one of the other source/drain regions in the individual pairs of recessed access devices;
• selectively depositing conductive material onto:
• the first upper end-walls of the individual conductive vias in the second series of rows relative to the second upper end-walls of the individual conductive vias in the second series of rows;
• and
• the second upper end-walls of the individual conductive vias in the first series of rows relative to the first upper end-walls of the individual conductive vias in the first series of rows;
• and
• forming a plurality of capacitors individually comprising a lower conductive electrode, an upper conductive electrode, and a capacitor insulator there-between;
• individual of the lower conductive electrodes being electrically coupled to the conductive material of the individual conductive vias that was selectively deposited.