DRAM Layout with Vertical FETS and Method of Formation
AssigneeMicron Technology, Inc.
InventorsTodd R. Abbott, Homer M. Manning
Life of this patent
Estimating the term…
Abstract
DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
Claims22
1-49. (canceled)
A semiconductor memory array comprising:
- a plurality of memory cells arranged into an array of rows and columns, wherein each memory cell comprises a vertical transistor having first, second and third conductive regions, wherein the third conductive region of the vertical transistor is electrically coupled to one electrode of a capacitor, at least one of the plurality of memory cells having an area of about 4F2, where F is the minimum lithographic feature size;
- a plurality of pairs of first and second bit lines located below the vertical transistors, wherein each pair of first and second bit lines is in contact with the first conductive region of each vertical transistor in a respective column;
- and
- a plurality of word lines, wherein each word line adjoins the second conductive region of each vertical transistor in a respective row, and is separated from the second conductive region by a gate insulating layer.
51-53. (canceled)
58-91. (canceled)
A semiconductor memory array comprising:
- a plurality of memory cells arranged into an array of rows and columns, wherein each memory cell comprises a vertical transistor having first, second and third conductive regions, wherein the third conductive region of the vertical transistor is electrically coupled to one electrode of a capacitor, at least one of the plurality of memory cells having an area of about 4F2, where F is the minimum lithographic feature size;
- a plurality of pairs of first and second bit lines located below the vertical transistors, wherein each pair of first and second bit lines is in contact with the first conductive region of each vertical transistor in a respective column;
- and
- a plurality of pairs of first and second word lines, wherein each pair of first and second word line adjoins the second conductive region of each vertical transistor in a respective row, and is separated from the second conductive region by a gate insulating layer.
Dependencies are inferred from the claim text.