Memory address decode array with vertical transistors
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Wendell P. Noble
Life of this patent
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Abstract
A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
Claims33
A decoder for a memory device, comprising:
- a number of address lines;
- a number of output lines;
- wherein the address lines, and the output lines form an array;
- and
- a number of vertical transistors that are selectively disposed at intersections of output lines and address lines, wherein each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistor, a gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines such that the transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
A memory device, comprising:
- an array of word lines and complementary bit line pairs;
- a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair;
- a row decoder that is coupled to the word lines so as to implement a logic function that selects one of the word lines responsive to an address provided to the row decoder;
- a number of sense amplifiers, each coupled to a complementary pair of bit lines;
- a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder;
- and
- wherein the row decoder comprises an array of vertical transistors that are formed in pillars of semiconductor material and that are selectively coupled to implement a logic function that selects a wordline based on a supplied address.
A computer system, comprising:
- a microprocessor;
- a memory device coupled to the microprocessor;
- and
- wherein the memory device comprises:
- an array of word lines and complementary bit line pairs;
- a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair;
- a row decoder that is coupled to the word lines so as to implement a logic function that selects an one of the word lines responsive to an address provided to the row decoder;
- a number of sense amplifiers, each coupled to a complementary pair of bit lines;
- a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder;
- and
- wherein the row decoder comprises an array of vertical transistors that are formed in pillars of semiconductor material and that are coupled to implement a logic function that selects a wordline or complementary bit line pair based on a supplied address.
Dependencies are inferred from the claim text.