Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry

A method of forming an array, comprising:

• forming rows of conductive vias over a substrate, individual of the conductive vias comprising first and second opposing upper end-walls;
• covering the first and second upper end-walls with a covering material;
• masking a first series of the rows with a first mask on the substrate to leave a second series of the rows unmasked;
• removing the covering material from and to expose the first upper end-walls in the unmasked second series of the rows while the first series of the rows is masked with the first mask;
• after removing the covering material from and to expose the first upper end-walls in the unmasked second series of the rows, removing the first mask and masking the second series of the rows with a second mask on the substrate to leave the first series of the rows unmasked;
• removing the covering material from and to expose the second upper end-walls in the unmasked first series of the rows while the second series of the rows is masked with the second mask;
• after removing the covering material from and to expose the second upper end-walls in the unmasked first series of the rows, removing the second mask;
• and
• after removing the first mask and the second mask and while the first and second series of the rows are exposed, selectively depositing a conductive material onto:
• the exposed first upper end-walls of the individual conductive vias in the second series of the rows relative to the covering material that covers the second upper end-walls of the individual conductive vias in the second series of the rows;
• and
• the exposed second upper end-walls of the individual conductive vias in the first series of the rows relative to the covering material that covers the first upper end-walls of the individual conductive vias in the first series of the rows.

A method used in the fabrication of integrated circuitry, comprising:

• forming an array of conductive vias in a first 2D horizontal lattice configuration, the array comprising a first series of rows of individual of the conductive vias and a second series of rows of the individual conductive vias, the individual vias comprising first and second opposing upper end-walls;
• selectively depositing a conductive material onto:
• the first upper end-walls of the individual conductive vias in the second series of rows relative to the second upper end-walls of the individual vias in the second series of rows;
• and
• the second upper end-walls of the individual conductive vias in the first series of rows relative to the first upper end-walls of the individual conductive vias in the first series of rows;
• and
• the selectively depositing forming a second 2D horizontal lattice configuration of the conductive material that is different from that of the first 2D horizontal lattice configuration.