H10P 32/302
Doping polycrystalline silicon or amorphous silicon layers
Official title: {Doping polycrystalline silicon or amorphous silicon layers}
H10P32/302 (Doping polycrystalline silicon or amorphous silicon layers) appears on 428 US grants and 304 published applications in this corpus.
Search patents in H10P- Granted patents
- 428
- Published applications
- 304
- Assignees
- 166
- Inventors
- 874
- Latest grant
- 20 Jan 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 4 | 0 |
| 1978 | 5 | 0 |
| 1979 | 8 | 0 |
| 1980 | 13 | 0 |
| 1981 | 11 | 0 |
| 1982 | 5 | 0 |
| 1983 | 6 | 0 |
| 1984 | 8 | 0 |
| 1985 | 9 | 0 |
| 1986 | 8 | 0 |
| 1987 | 10 | 0 |
| 1988 | 11 | 0 |
| 1989 | 3 | 0 |
| 1990 | 6 | 0 |
| 1991 | 7 | 0 |
| 1992 | 3 | 0 |
| 1993 | 10 | 0 |
| 1994 | 8 | 0 |
| 1995 | 8 | 0 |
| 1996 | 3 | 0 |
| 1997 | 7 | 0 |
| 1998 | 5 | 0 |
| 1999 | 7 | 0 |
| 2000 | 6 | 0 |
| 2001 | 4 | 1 |
| 2002 | 5 | 5 |
| 2003 | 4 | 5 |
| 2004 | 3 | 7 |
| 2005 | 5 | 4 |
| 2006 | 3 | 6 |
| 2007 | 3 | 8 |
| 2008 | 5 | 10 |
| 2009 | 3 | 8 |
| 2010 | 5 | 9 |
| 2011 | 8 | 7 |
| 2012 | 5 | 11 |
| 2013 | 11 | 10 |
| 2014 | 10 | 14 |
| 2015 | 9 | 11 |
| 2016 | 18 | 16 |
| 2017 | 16 | 13 |
| 2018 | 13 | 19 |
| 2019 | 24 | 32 |
| 2020 | 24 | 26 |
| 2021 | 16 | 19 |
| 2022 | 20 | 24 |
| 2023 | 12 | 10 |
| 2024 | 14 | 12 |
| 2025 | 14 | 11 |
| 2026 | 1 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method for manufacturing gate of NAND flash20 Jan 2026US 12,532,525 B2Shanghai Huali Integrated Circuit Corporation
- Ion implantation for reduced hydrogen incorporation in amorphous silicon11 Nov 2025US 12,469,700 B2APPLIED Materials.Inc.
- Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells4 Nov 2025US 12,464,718 B2
- Polysilicon resistors with high sheet resistance4 Nov 2025US 12,464,737 B2Texas Instruments Incorporated
- Semiconductor device structure including composite interconnect28 Oct 2025US 12,456,684 B2Nanya Technology Corporation
- Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells24 Sep 2026US 2026/0293133 A1Lodestar Licensing Group LLC
- Sidewall doping method for 3d memory device9 Jul 2026US 2026/0198240 A1Chengdu Pbm Technology Ltd.
- Semiconductor device and method of fabricating the same16 Apr 2026US 2026/0107723 A1Gigadevice Semiconductor Inc.
- Transistor having a gate region with a uniform gate length and a body contact region abutted to a conduction channel under the gate region to improve mitigation of the kink effect26 Mar 2026US 2026/0090065 A1QUALCOMM Incorporated
- Electrostatic clamping of glass substrates5 Mar 2026US 2026/0068555 A1
Most cited
By later US patents
- Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases229US 6,479,373 B2Infineon Technologies AG · 2002
- Means for stabilizing polycrystalline semiconductor layers175US 4,755,865 AMotorola, Inc. · 1988
- Thin film FET doped with diffusion inhibitor142US 4,772,927 AHitachi, Ltd. · 1988
- Anisotropic gap etch129US 9,502,258 B2APPLIED Materials.Inc. · 2016
- Method for manufacturing a semiconductor device113US 4,309,224 ATokyo Shibaura Denki Kabushiki Kaisha · 1982