Method for manufacturing gate of NAND flash

A method for manufacturing a NAND flash, wherein a storage area of the flash includes multiple memory cells, and the formation of each memory cell includes the following steps:

• step 1, forming a plurality of field oxides on a semiconductor substrate, the field oxides isolating a plurality of active areas, and
• sequentially form a floating gate dielectric layer and a first polysilicon layer on the surface of an active area, the first polysilicon layer being used to form a polysilicon floating gate;
• step 2, sequentially forming an inter-gate dielectric layer and a second polysilicon layer, the inter-gate dielectric layer covering the surface of the first polysilicon layer and the surface of the field oxide, the second polysilicon layer being formed on the surface of the inter-gate dielectric layer, the second polysilicon layer being used to form a polysilicon control gate, the second polysilicon layer having a first doping concentration, the polysilicon control gate having a target doping concentration, the first doping concentration being less than the target doping concentration, and the first doping concentration is used to control the lateral etching of the polycrystalline silicon control gate in subsequent gate etching;
• step 3, forming a pattern transfer mask layer composed of a plurality of mask sublayers with different etching rates on the surface of the second polysilicon layer;
• step 4, defining a formation area of the polysilicon control gate, and sequentially etching the mask sublayers of the pattern transfer mask layer outside the formation area of the polysilicon control gate to achieve patterning of the pattern transfer mask layer;
• step 5, performing gate etching, comprising:
• sequentially etching the second polysilicon layer, the inter-gate dielectric layer, and the first polysilicon layer by using the patterned pattern transfer mask layer as a mask, wherein
• the polysilicon control gate is composed of the second polysilicon layer subjected to the gate etching, the polysilicon floating gate is composed of the first polysilicon layer subjected to the gate etching, each of the memory cells has a first gate structure, the first gate structure is formed by stacking the floating gate dielectric layer formed on the surface of the active area, the polysilicon floating gate, the inter-gate dielectric layer, and the polysilicon control gate, and a first interval area is provided between the first gate structures;
• during processes of etching the inter-gate dielectric layer and the first polysilicon layer, the side surface of the polysilicon control gate is exposed and laterally etched to reduce the width of the polysilicon control gate, the first doping concentration controls the lateral etching amount of the polysilicon control gate;
• step 6, forming a first spacer, wherein in the storage area, the first spacer is formed on the side surface of the first gate structure and fully fills the first interval area;
• and
• step 7, adjusting a thickness of the pattern transfer mask layer on the top of the polysilicon control gate by using the first spacer as a self-aligned mask, and then performing self-aligned ion implantation, wherein due to the self-aligned ion implantation, a dopant is implanted into the polysilicon control gate after passing through the pattern transfer mask layer, and the self-aligned ion implantation increases a doping concentration of the polysilicon control gate to the target doping concentration.