With a digital phase-locked loop [pll] processing binary samples

Official title: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}

H04L7/0331 (With a digital phase-locked loop [pll] processing binary samples) appears on 1,407 US grants and 950 published applications in this corpus.