Electronic digital system comprising a serializer deserializer module, serializer deserializer module and method of control

An electronic digital system, comprising:

• a digital core;
• a Serializer Deserializer module;
• said digital core comprising a first in first out (FIFO) architecture device that is written to with a write clock and configured to transmit parallel data, and read from with a read clock, on a set of buses coupled to said Serializer Deserializer module;
• said Serializer Deserializer module configured to transmit said parallel data read from said FIFO architecture device as a corresponding set of serial signals transmitted by a respective set of transmitters, said set of serial signals and the corresponding set of transmitters being logically grouped according to one or more clusters corresponding to one or more groups of buses;
• said set of transmitters comprising respective independent phase lock loop (PLL) circuits issuing respective PLL clock signals, using as reference a cluster transmitter reference clock common to a respective cluster of transmitters controlling a frequency of serialization operation of said transmitters and a set of low frequency clock signals obtained by said PLL clock signals through frequency division;
• a digital frequency correction module configured to supply to each independent PLL circuit a data strobe encoded frequency correction signal specifying a frequency correction dependent on a detected phase error, between the write clock and the read clock, said read clock corresponding to one low frequency clock signal of said set of low frequency clock signals;
• said digital frequency correction module comprising one or more cluster digital frequency correction sub-modules each corresponding to a respective cluster, clocked by a respective cluster clock signal, corresponding to said cluster transmitter reference clock, configured to receive and process a respective data strobe encoded cluster frequency correction comprising said frequency correction dependent on the detected phase error, outputting a respective correction signal from which data strobe encoded frequency correction signals for each of said transmitters are obtained by demultiplexing;
• wherein each of said transmitters is configured to assert respective acknowledge signals when receiving said respective data strobe encoded frequency correction signals specifying a frequency correction;
• and
• wherein each cluster digital frequency correction sub-module comprises a handshake module receiving a set of said acknowledge signals by the transmitters of the cluster, which are resynchronized with said cluster clock signal, said handshake module being configured to issue said output data strobe encoded frequency correction signal as asserted to specify frequency correction of the respective transmitters upon receival of a set of de-asserted acknowledge signals, resynchronized with said cluster clock signal, from all enabled transmitters of the cluster, said transmitters being configured to de-assert said acknowledge signals upon completion of a number of cycles of a frequency correction on the frequency of all the independent PLL circuits of the corresponding cluster.