Feedforward jitter correction
AssigneeMellanox Technologies, Ltd.
InventorJohan Jacob Mohr
Life of this patent
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Abstract
Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.
Claims20
A serializer/deserializer (SerDes) integrated circuit (IC) comprising:
- a clock-recovery circuit comprising a phase detector to determine phase information about a transmit clock used to transmit a signal to the SerDes IC;
- and
- a feedforward jitter correction circuit coupled to the clock-recovery circuit, wherein the clock-recovery circuit is to control a receiver sampling clock in a closed-loop fashion using the phase information, wherein the feedforward jitter correction circuit is to control, using the phase information, a re-sampling clock in an open-loop fashion to compensate for sampling jitter above a loop bandwidth of the clock-recovery circuit.
A method of operating a serializer/deserializer (SerDes) integrated circuit (IC), the method comprising:
- determining, using a phase detector of a clock-recovery circuit, phase information about a transmit clock used to transmit an incoming signal to the SerDes IC;
- controlling, using the clock-recovery circuit and the phase information, a receiver sampling clock in a closed-loop fashion;
- and
- controlling, using a feedforward jitter correction circuit and the phase information, a re-sampling clock in an open-loop fashion to compensate for sampling jitter above a loop bandwidth of the clock-recovery circuit.
A communication system comprising:
- a serializer/deserializer (SerDes) receiver, wherein the SerDes receiver comprises:
- a clock-recovery circuit comprising a phase detector to determine phase information about a transmit clock used to transmit a signal to the SerDes receiver;
- and
- a feedforward jitter correction circuit coupled to the clock-recovery circuit, wherein the clock-recovery circuit is to control a receiver sampling clock in a closed-loop fashion using the phase information, wherein the feedforward jitter correction circuit is to control, using the phase information, a re-sampling clock in an open-loop fashion to compensate for sampling jitter above a loop bandwidth of the clock-recovery circuit.
Dependencies are inferred from the claim text.