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US 2026/0149557 A1Published application
Clock and data recovery (cdr) circuitry utilizing blind sampling
AssigneeProtocol Insight, LLC
InventorsAnthony Carosa, Aleksey Tyshchenko, Edward Brush, Scott Masepohl, David Halupka
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Abstract
A method, system, and apparatus for digital clock and data recovery (CDR) with analog signal that samples blindly (i.e., independent of the baud rate). The CDR further has a digital monolithic circuit that includes an interpolator circuit, and a fully digital clock (FDC) that recovers the digital data from the analog signal.
Claims19
A digital clock and data recovery (CDR) system, comprising:
- a blind sampling circuit that receives an input sampled signal;
- and
- a digital monolithic circuit that includes:
- a phase detector (PD) that determines a phase error which is used to determine a unit interval (UI) center;
- and
- a fully digital clock (FDC) that creates a digital clock used to recover digital data from the input sampled signal.
3 more elements
A method for sampling an analog input signal, comprising:
- receiving an input sampled signal at a blind sampling circuit;
- and
- recovering digital data from the input sampled signal using a phase detector (PD) that determines a phase error which is used to determine a unit interval (UI) center and a fully digital clock (FDC) that creates a digital clock used to recover digital data from the input sampled signal.
Dependencies are inferred from the claim text.